MC100LVEL56: Multiplexer, 2:1 Differential, Dual ECL, 3.3 V _ BDTIC 中国领先电子元器件代理商

MC100LVEL56: Multiplexer, 2:1 Differential, Dual ECL, 3.3 V

The MC100LVEL56 is a dual, fully differential 2:1 multiplexer. The differential data path makes the device ideal for multiplexing low skew clock or other skew sensitive signals. The device features both individual and common select inputs to address both data path and random logic applications. The differential inputs have special circuitry which ensures device stability under open input conditions. When both differential inputs are left open the D input will pull down to VEE. The Dbar input will bias around VCC/2 forcing the Q output LOW. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 5F capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open.

特性

440ps Typical Propagation Delays
Separate and Common Select
ESD Protection: >2 KV HBM
The 100 Series Contains Temperature Compensation
PECL Mode Operating Range: VCC = 3.0 V to 3.8 V with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -3.8 V
Internal Input 75 K ohm Pulldown Resistors
Q Output will Default LOW with Inputs Open or at VEE
Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
Flammability Rating: UL-94 code V-0 @ 1/8", Oxygen Index 28 to 34
Transistor Count = 147 devices
Pb-Free Packages are Available

封装

应用注释 (15)

Document Title	Document ID/Size	Revision	Revision Date
AC Characteristics of ECL Devices	AND8090/D (896.0kB)	1
Clock Generation and Clock and Data Marking and Ordering Information Guide	AND8002/D (71kB)	12
Clock Management Design Using Low Skew and Low Jitter Devices	TND301/D (205.0kB)	0
Designing with PECL (ECL at +5.0 V)	AN1406/D (105.0kB)	2
ECL Clock Distribution Techniques	AN1405/D (54.0kB)	1
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide	AND8002 (71kB)	12
Interfacing Between LVDS and ECL	AN1568/D (121.0kB)	11
Interfacing with ECLinPS	AND8066/D (72kB)	3
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks	AND8001/D (90.0kB)	0
Phase Lock Loop General Operations	AND8040/D (64.0kB)	3
Storage and Handling of Drypack Surface Mount Device	AND8003/D (49kB)	2	Mar, 2016
Termination of ECL Logic Devices	AND8020/D (176.0kB)	6
The ECL Translator Guide	AN1672/D (142.0kB)	12
Thermal Analysis and Reliability of WIRE BONDED ECL	AND8072/D (119.0kB)	5
Using Wire-OR Ties in ECLInPS™ Designs	AN1650/D (1130.0kB)	3

数据表 (1)

Document Title	Document ID/Size	Revision	Revision Date
3.3V ECL Dual Differential 2:1 Multiplexer	MC100LVEL56/D (149kB)	13	Jul, 2016

仿真模型 (4)

Document Title	Document ID/Size	Revision
IBIS Model for mc100lvel56dw -3.3V	MC100LVEL56DW_-33.IBS (15.0kB)	4
IBIS Model for mc100lvel56dw 3.3V	MC100LVEL56DW_33.IBS (15.0kB)	4
Low Voltage ECLinPS SPICE Modeling Kit	AN1560/D (88.0kB)	5
MECL 10H SPICE Kit for Berkeley SPICE (PSPICE)	AN1578/D (161.0kB)	0

封装图纸 (1)

Document Title	Document ID/Size	Revision
SOIC-20 WB	751D-05 (36.3kB)	H

产品订购型号

产品	状况	Compliance	封装		MSL*	容器		预算价格 (1千个数量的单价）
MC100LVEL56DWG	Active	Pb-free Halide free	SOIC-20W	751D-05	3	Tube	38	联系BDTIC
MC100LVEL56DWR2G	Active	Pb-free Halide free	SOIC-20W	751D-05	3	Tape and Reel	1000	联系BDTIC