MC10EP29: 3.3 V / 5.0 V ECL Dual Differential Clock/Data D Flip-Flop With Set and Reset

The MC10/100EP29 is a dual master-slave flip flop. The device features fully differential Data and Clock inputs as well as outputs. The MC10/100EP29 is functionally equivalent to the MC10/100EL29. Data enters the master latch when the clock is LOW and transfers to the slave upon a positive transition on the clock input.The differential inputs have special circuitry which ensures device stability under open input conditions. When both differential inputs are left open the Dbar input will pull down to VEE and the Dbar input will bias around VCC/2. The outputs will go to a defined state, however the state will be random based on how the flip flop powers up.Both flip flops feature asynchronous, overriding Set and Reset inputs. Note that the Set and Reset inputs cannot both be HIGH simultaneously.The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01uF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open.The 100 Series Contains Temperature Compensation

特性

Maximum Frequency > 3 GHz Typical
500 ps Typical Propagation Delays
PECL Mode Operating Range: VCC = 3.0 V to 5.5 V with VEE = 0 V
NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -5.5 V
Open Input Default State
Safety Clamp on Inputs
These are Pb−Free Devices

应用

Functionally equivalent to the MC10/100EL29

封装

应用注释 (14)

Document Title	Document ID/Size	Revision	Revision Date
AC Characteristics of ECL Devices	AND8090/D (896.0kB)	1
Clock Generation and Clock and Data Marking and Ordering Information Guide	AND8002/D (71kB)	12
Designing with PECL (ECL at +5.0 V)	AN1406/D (105.0kB)	2
ECL Clock Distribution Techniques	AN1405/D (54.0kB)	1
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide	AND8002 (71kB)	12
Interfacing Between LVDS and ECL	AN1568/D (121.0kB)	11
Interfacing with ECLinPS	AND8066/D (72kB)	3
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks	AND8001/D (90.0kB)	0
Phase Lock Loop General Operations	AND8040/D (64.0kB)	3
Storage and Handling of Drypack Surface Mount Device	AND8003/D (49kB)	2	Mar, 2016
Termination of ECL Logic Devices	AND8020/D (176.0kB)	6
The ECL Translator Guide	AN1672/D (142.0kB)	12
Thermal Analysis and Reliability of WIRE BONDED ECL	AND8072/D (119.0kB)	5
Using Wire-OR Ties in ECLInPS™ Designs	AN1650/D (1130.0kB)	3

数据表 (1)

Document Title	Document ID/Size	Revision	Revision Date
3.3V / 5V ECL Dual Differential Data and Clock D Flip-Flop With Set and Reset	MC10EP29/D (105kB)	9	Apr, 2014

仿真模型 (4)

Document Title	Document ID/Size	Revision
IBIS Model for mc10ep29dt -3.3V	MC10EP29DT_-33.IBS (6.0kB)	2
IBIS Model for mc10ep29dt 3.3V	MC10EP29DT_33.IBS (6.0kB)	1
IBIS Model for mc10ep29dt 5.0V	MC10EP29DT_50.IBS (6.0kB)	1
IBSI Model for mc10ep29dt -5.0V	MC10EP29DT_-50.IBS (6.0kB)	1

封装图纸 (2)

Document Title	Document ID/Size	Revision
QFN20, 4x4, 0.5P	485E-01 (60.9kB)	B
TSSOP-20 WB	948E-02 (39.7kB)	D

产品订购型号

产品	状况	Compliance	封装		MSL*	容器		预算价格 (1千个数量的单价）
MC10EP29DTG	Active	Pb-free Halide free	TSSOP-20	948E-02	1	Tube	75	联系BDTIC
MC10EP29DTR2G	Lifetime	Pb-free Halide free	TSSOP-20	948E-02	1	Tape and Reel	2500
MC10EP29MNG	Active	Pb-free Halide free	QFN-20	485E-01	1	Tube	92	联系BDTIC
MC10EP29MNTXG	Lifetime	Pb-free Halide free	QFN-20	485E-01	1	Tape and Reel	3000