MC10EP35: 3.3 V / 5.0 V ECL JK Flip-Flop

The MC10EP35 is a higher speed/low voltage version of the EL35 JK flip flop. The JK data enters the master portion of the flip flop when the clock is LOW and is transferred to the slave, and thus the outputs, upon a positive transition of the clock. The reset pin is asynchronous and is activated with a logic HIGH.The 100 Series contains temperature compensation.

特性
  • 410 ps Propagation Delay
  • Maximum Frequency > 3 GHz Typical
  • PECL Mode Operatio Range: VCC = 3.0 V to 5.5 V with VEE = 0 V
  • NECL Mode Operating Range: VCC = 0 V with VEE = -3.0V to -5.5V
  • Open Input Default State
  • Q Output will default LOW with inputs open or at VEE
  • Pb-Free Packages are Available
应用
  • Using ECL Logic technologies for reducing system clock skew over the alternative CMOS and TTL technologies.
应用注释 (11)
Document TitleDocument ID/SizeRevisionRevision Date
AC Characteristics of ECL DevicesAND8090/D (896.0kB)1
Clock Generation and Clock and Data Marking and Ordering Information GuideAND8002/D (66kB)11
Designing with PECL (ECL at +5.0 V)AN1406/D (105.0kB)2
ECL Clock Distribution TechniquesAN1405/D (54.0kB)1
ECLinPS Plus™ Spice Modeling KitAND8009/D (343.0kB)11
Interfacing Between LVDS and ECLAN1568/D (121.0kB)11
Interfacing with ECLinPS™AND8066/D (58.0kB)2
Metastability and the ECLinPS FamilyAN1504/D (103.0kB)3
Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksAND8001/D (90.0kB)0
Termination of ECL Logic DevicesAND8020/D (176.0kB)6
The ECL Translator GuideAN1672/D (142.0kB)12
封装图纸 (2)
Document TitleDocument ID/SizeRevision
SOIC-8 Narrow Body751-07 (62.6kB)AK
TSSOP 8 3.0x3.0x0.95 mm948R-02 (77.3kB)A
数据表 (1)
Document TitleDocument ID/SizeRevisionRevision Date
3.3V / 5V ECL JK Flip FlopMC10EP35/D (137.0kB)6
产品订购型号
产品状况Compliance具体说明封装MSL*容器预算价格 (1千个数量的单价）
MC10EP35DGActivePb-free Halide free3.3 V / 5.0 V ECL JK Flip-FlopSOIC-8751-071Tube98联系BDTIC
MC10EP35DR2GActivePb-free Halide free3.3 V / 5.0 V ECL JK Flip-FlopSOIC-8751-071Tape and Reel2500联系BDTIC
MC10EP35DTGActivePb-free Halide free3.3 V / 5.0 V ECL JK Flip-FlopTSSOP-8948R-023Tube100联系BDTIC
MC10EP35DTR2GActivePb-free Halide free3.3 V / 5.0 V ECL JK Flip-FlopTSSOP-8948R-023Tape and Reel2500联系BDTIC
订购产品技术参数
ProductTypeBitsInput LevelOutput LevelVCC Typ (V)tJitter Typ (ps)tpd Typ (ns)tsu Min (ns)th Min (ns)trec Typ (ns)tR & tF Max (ps)fToggle Typ (MHz)
MC10EP35DGJK-Type1CML   ECLECL3.3   50.20.410.150.150.091703000
MC10EP35DR2GJK-Type1CML   ECLECL3.3   50.20.410.150.150.091703000
MC10EP35DTGJK-Type1CML   ECLECL3.3   50.20.410.150.150.091703000
MC10EP35DTR2GJK-Type1CML   ECLECL3.3   50.20.410.150.150.091703000
3.3 V / 5 V ECL JK Flip Flop (174kB) MC100EP35
AC Characteristics of ECL Devices NB100LVEP91
Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91
Designing with PECL (ECL at +5.0 V) NB100LVEP91
ECL Clock Distribution Techniques NB100LVEP91
ECLinPS Plus™ Spice Modeling Kit MC10EPT20
Interfacing Between LVDS and ECL NB100ELT23L
Interfacing with ECLinPS NB100LVEP91
Metastability and the ECLinPS Family MC10EPT20
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks NUP4201
Termination of ECL Logic Devices NB100LVEP91
The ECL Translator Guide NB100LVEP91
SOIC-8 Narrow Body CM1216
TSSOP 8 3.0x3.0x0.95 mm NB100ELT23L
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