MC10H164: 8-Line Multiplexer

The MC10H164 is a MECL 10H part which is a functional/pinout duplication of the standard MECL 10K family part, with 100% improvement in propagation delay, and no increase in power supply current. The MC10H164 is designed to be used in data multiplexing and parallel to serial conversion applications. Full parallel gating provides equal delays through any data path. The MC10H164 incorporates an output buffer, eight inputs and an enable. A high on the enable forces the output low. The open emitter output allows the MC10H164 to be connected directly to a data bus. The enable line allows an easy means of expanding to more than 8 lines using additional MC10H164's.

特性
  • Propagation Delay, 1.0 ns Typical
  • Power Dissipation, 310 mW Typical (same as MECL 10K)
  • Improved Noise Margin 150 mV (Over Operating Voltage and Temperature Range)
  • Voltage Compensated
  • MECL 10K Compatible
  • Pb-Free Packages are Available
应用注释 (16)
Document TitleDocument ID/SizeRevisionRevision Date
AC Characteristics of ECL DevicesAND8090/D (896.0kB)1
Clock Generation and Clock and Data Marking and Ordering Information GuideAND8002/D (71kB)12
Clock Management Design Using Low Skew and Low Jitter DevicesTND301/D (205.0kB)0
Designing with PECL (ECL at +5.0 V)AN1406/D (105.0kB)2
ECL Clock Distribution TechniquesAN1405/D (54.0kB)1
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuideAND8002 (71kB)12
Family Characteristics for MECL 10H™ and MECL 10K™TND309/D (248.0kB)1
Interfacing Between LVDS and ECLAN1568/D (121.0kB)11
Interfacing with ECLinPSAND8066/D (72kB)3
Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksAND8001/D (90.0kB)0
Phase Lock Loop General OperationsAND8040/D (64.0kB)3
Storage and Handling of Drypack Surface Mount DeviceAND8003/D (49kB)2Mar, 2016
Termination of ECL Logic DevicesAND8020/D (176.0kB)6
The ECL Translator GuideAN1672/D (142.0kB)12
Thermal Analysis and Reliability of WIRE BONDED ECLAND8072/D (119.0kB)5
Using Wire-OR Ties in ECLInPS™ DesignsAN1650/D (1130.0kB)3
数据表 (1)
Document TitleDocument ID/SizeRevisionRevision Date
8-Line MultiplexerMC10H164/D (141kB)9Aug, 2016
仿真模型 (2)
Document TitleDocument ID/SizeRevisionRevision Date
IBIS Model for MC10H164LMC10H164L.IBS (6.0kB)0
IBIS Model for MC10H164PMC10H164P.IBS (6.0kB)0
封装图纸 (2)
Document TitleDocument ID/SizeRevision
20 LEAD PLLC775-02 (60.9kB)F
PDIP-16648-08 (34.2kB)V
产品订购型号
产品状况Compliance封装MSL*容器预算价格 (1千个数量的单价）
MC10H164FNGLast ShipmentsPb-free Halide freePLLC-20775-023Tube46
MC10H164FNR2GActivePb-free Halide freePLLC-20775-023Tape and Reel500联系BDTIC
MC10H164PGActivePb-free Halide freePDIP-16648-08NATube25联系BDTIC
订购产品技术参数
ProductInput/Output RatioChannelsInput LevelOutput LevelVCC Typ (V)fMax Typ (MHz)tJitter Typ (ps)tskew(OO) Max (ps)tpd Typ (ns)
MC10H164FNR2G8:11ECLECL-5.21
MC10H164PG8:11ECLECL-5.21
8-Line Multiplexer (141kB) MC10H164
AC Characteristics of ECL Devices NB100LVEP91
Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91
Clock Management Design Using Low Skew and Low Jitter Devices MC10H604
Designing with PECL (ECL at +5.0 V) NB100LVEP91
ECL Clock Distribution Techniques NB100LVEP91
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide NB100LVEP91
Family Characteristics for MECL 10H™ and MECL 10K™ MC10H604
Interfacing Between LVDS and ECL NB100ELT23L
Interfacing with ECLinPS NB100LVEP91
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks NUP4201
Phase Lock Loop General Operations MC10H604
Storage and Handling of Drypack Surface Mount Device NB3U23C
Termination of ECL Logic Devices NB100LVEP91
The ECL Translator Guide NB100LVEP91
Thermal Analysis and Reliability of WIRE BONDED ECL NB100LVEP91
Using Wire-OR Ties in ECLInPS™ Designs MC10H351
IBIS Model for MC10H164L MC10H164
IBIS Model for MC10H164P MC10H164
20 LEAD PLLC MC10H351
PDIP-16 MC10H350
Products 产品服务
Manufacturers 生产厂家
联系购买Sales
©1993 - 2024 BDTIC