MC10H602: 9-Bit Latch/TTL-ECL Translator

The MC10H/100H602 is a 9-bit, dual supply TTL to ECL translator with latch. Devices in the 9-bit translator series utilize the 28-lead PLCC for optimal power pinning, signal flow-through and electrical performance. The H602 features D-type latches. Latching is controlled by Latch Enable (LEN), while the Master Reset input resets the latches. A post-latch logic enable is also provided (ENECL), allowing control of the output state without destroying latch data. All control inputs are ECL level. The 10H version is compatible with MECL 10H ECL logic levels. The 100H version is compatible with 100K levels.

特性
  • 9-Bit Ideal for Byte-Parity Applications
  • Flow-Through Configuration
  • Extra TTL and ECL Power/Ground Pins to Minimize Switching Noise
  • Dual Supply
  • 3.5 ns Max D to Q
  • PNP TTL Inputs for Low Loading
  • Pb-Free Packages are Available
封装
应用注释 (15)
Document TitleDocument ID/SizeRevisionRevision Date
AC Characteristics of ECL DevicesAND8090/D (896.0kB)1
Clock Management Design Using Low Skew and Low Jitter DevicesTND301/D (205.0kB)0
Designing with PECL (ECL at +5.0 V)AN1406/D (105.0kB)2
ECL Clock Distribution TechniquesAN1405/D (54.0kB)1
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuideAND8002 (71kB)12
Family Characteristics for MECL 10H™ and MECL 10K™TND309/D (248.0kB)1
Interfacing Between LVDS and ECLAN1568/D (121.0kB)11
Interfacing with ECLinPSAND8066/D (72kB)3
MC10/100H60x Translator Family I/O SPICE Modelling KitAN1402/D (159.0kB)3
Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksAND8001/D (90.0kB)0
Phase Lock Loop General OperationsAND8040/D (64.0kB)3
Storage and Handling of Drypack Surface Mount DeviceAND8003/D (49kB)2Mar, 2016
Termination of ECL Logic DevicesAND8020/D (176.0kB)6
The ECL Translator GuideAN1672/D (142.0kB)12
Thermal Analysis and Reliability of WIRE BONDED ECLAND8072/D (119.0kB)5
封装图纸 (1)
Document TitleDocument ID/SizeRevision
28 LEAD PLCC776-02 (67.7kB)F
数据表 (1)
Document TitleDocument ID/SizeRevisionRevision Date
9-Bit Latch TTL/ECL TranslatorMC10H602/D (112.0kB)10
产品订购型号
产品状况Compliance封装MSL*容器预算价格 (1千个数量的单价）
MC10H602FNGActivePb-free Halide freePLCC-28776-023Tube37联系BDTIC
订购产品技术参数
ProductChannelsInput LevelOutput LevelVCC Typ (V)fMax Typ (MHz)tpd Typ (ns)tR & tF Max (ps)
MC10H602FNG1TTLECL52.351500
9-Bit Latch TTL/ECL Translator (112.0kB) MC10H602
AC Characteristics of ECL Devices NB100LVEP91
Clock Management Design Using Low Skew and Low Jitter Devices MC10H604
Designing with PECL (ECL at +5.0 V) NB100LVEP91
ECL Clock Distribution Techniques NB100LVEP91
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide NB100LVEP91
Family Characteristics for MECL 10H™ and MECL 10K™ MC10H604
Interfacing Between LVDS and ECL NB100ELT23L
Interfacing with ECLinPS NB100LVEP91
MC10/100H60x Translator Family I/O SPICE Modelling Kit MC10H604
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks NUP4201
Phase Lock Loop General Operations MC10H604
Storage and Handling of Drypack Surface Mount Device NB3U23C
Termination of ECL Logic Devices NB100LVEP91
The ECL Translator Guide NB100LVEP91
Thermal Analysis and Reliability of WIRE BONDED ECL NB100LVEP91
28 LEAD PLCC MC10H604
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