MC10H605: REG Hex ECL/TTL Translator

The MC10/100H605 is a 6-bit, registered, dual supply ECL to TTL translator. The device features differential ECL inputs for both data and clock. The TTL outputs feature balanced 24mA sink/source capabilities for driving transmission lines. With its differential ECL inputs and TTL outputs the H605 device is ideally suited for the receive function of a HPPI bus type board-to board interface application. The on chip registers simplify the task of synchronizing the data between the two boards. A VBB reference voltage is supplied for use with single ended data or clock. For single-ended applications the VBB output should be connected to the "bar" inputs (Dn or CLK) and bypassed to ground via a 0.01uF capacitor. To minimize the skew of the device differential clocks should be used. The ECL level Master Reset pin is asynchronous and common to all flip-flops. A "HIGH" on the Master Reset forces the Q outputs "LOW". The device is available in either ECL standard: the 10H device is compatible with MECL 10H logic levels while the 100H device is compatible with 100K logic levels.

特性
  • Differential ECL Data and Clock Inputs
  • 24mA Sink, 24mA Source TTL Outputs
  • Dual Power Supply
  • Multiple Power and Ground Pins to Minimize Noise
  • 2.0ns Part-to-Part Skew
  • Pb-Free Packages are Available
应用注释 (14)
Document TitleDocument ID/SizeRevisionRevision Date
AC Characteristics of ECL DevicesAND8090/D (896.0kB)1
Clock Management Design Using Low Skew and Low Jitter DevicesTND301/D (205.0kB)0
Designing with PECL (ECL at +5.0 V)AN1406/D (105.0kB)2
ECL Clock Distribution TechniquesAN1405/D (54.0kB)1
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuideAND8002 (66kB)11
Family Characteristics for MECL 10H™ and MECL 10K™TND309/D (248.0kB)1
Interfacing with ECLinPS™AND8066/D (58.0kB)2
MC10/100H60x Translator Family I/O SPICE Modelling KitAN1402/D (159.0kB)3
Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksAND8001/D (90.0kB)0
Phase Lock Loop General OperationsAND8040/D (64.0kB)3
Storage and Handling of Drypack Surface Mount DeviceAND8003/D (106.0kB)1
Termination of ECL Logic DevicesAND8020/D (176.0kB)6
The ECL Translator GuideAN1672/D (142.0kB)12
Thermal Analysis and Reliability of WIRE BONDED ECLAND8072/D (119.0kB)5
封装图纸 (1)
Document TitleDocument ID/SizeRevision
28 LEAD PLCC776-02 (67.7kB)F
数据表 (1)
Document TitleDocument ID/SizeRevisionRevision Date
Registered Hex ECL/TTL TranslatorMC10H605/D (137.0kB)8
产品订购型号
产品状况Compliance具体说明封装MSL*容器预算价格 (1千个数量的单价)
MC10H605FNGActivePb-free Halide freeREG Hex ECL/TTL TranslatorPLCC-28776-023Tube37联系BDTIC
订购产品技术参数
ProductChannelsInput LevelOutput LevelVCC Typ (V)fMax Typ (MHz)tpd Typ (ns)tR & tF Max (ps)
MC10H605FNG6ECLTTL55.21500
Registered Hex ECL/TTL Translator MC10H605
AC Characteristics of ECL Devices NB100LVEP91
Clock Management Design Using Low Skew and Low Jitter Devices MC10H604
Designing with PECL (ECL at +5.0 V) NB100LVEP91
ECL Clock Distribution Techniques NB100LVEP91
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide NB100LVEP91
Family Characteristics for MECL 10H™ and MECL 10K™ MC10H604
Interfacing with ECLinPS NB100LVEP91
MC10/100H60x Translator Family I/O SPICE Modelling Kit MC10H604
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks NUP4201
Phase Lock Loop General Operations MC10H604
Storage and Handling of Drypack Surface Mount Device NB3U23C
Termination of ECL Logic Devices NB100LVEP91
The ECL Translator Guide NB100LVEP91
Thermal Analysis and Reliability of WIRE BONDED ECL NB100LVEP91
28 LEAD PLCC MC10H604