NB100LVEP222: Clock / Data Fanout Buffer, 2:1:15 Differential, ÷1 / ÷2, ECL / PECL, 2.5 V / 3.3 V

The NB100LVEP222 is a low skew 2:1:15 differential div 1/div 2 ECL fanout buffer designed with clock distribution in mind. The LVECL/LVPECL input signal pairs can be used in a differential configuration or single-ended (with VBB output reference bypassed and connected to the unused input of a pair). Either of two fully differential clock inputs may be selected. Each of the four output banks of 2, 3, 4, and 6 differential pairs may be independently configured to fanout 1X or 1/2X of the input frequency. When the output banks are configured with the div 1 mode, data can also be distributed. The LVEP222 specifically guarantees low output to output skew. Optimal design, layout, and processing minimize skew within a device and from lot to lot. This device is an improved version of the MC100LVE222 with higher speed capability and reduced skew. The fsel pins and CLK_Sel pin are asynchronous control inputs. Any changes may cause indeterminate output states requiring an MR pulse to resynchronize any 1/2X outputs (See Figure 4). Unused output pairs should be left unterminated (open) to reduce power and switching noise. The NB100LVEP222, as with most ECL devices, can be operated from a positive VCC/VCC0 supply in LVPECL mode. This allows the LVEP222 to be used for high performance clock distribution in 2.5/3.3 V systems. In a PECL environment series or Thevenin line, terminations are typically used as they require no additional power supplies. For more information on using PECL, designers should refer to Application Note AN1406/D. For a SPICE model, refer to Application Note AN1560/D. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended LVPECL input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC/VCC0 via a 0.01 uF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open

特性
  • 20 ps Output-to-Output Skew
  • 85 ps Part-to-Part Skew
  • Selectable 1x or 1/2x Frequency Outputs
  • LVPECL Mode Operating Range: VCC= 2.375 V to 3.8 V with VEE = 0 V
  • NECL Mode Operating Range: VCC = 0 V with VEE = -2.375 V to -3.8 V
  • Internal Input Pulldown Resistors
  • Performance Upgrade to ON Semiconductor's MC100LVE222
  • VBB Output
应用
  • Clock Distribution
封装
应用注释 (13)
Document TitleDocument ID/SizeRevisionRevision Date
AC Characteristics of ECL DevicesAND8090/D (896.0kB)1
Clock Generation and Clock and Data Marking and Ordering Information GuideAND8002/D (71kB)12
Designing with PECL (ECL at +5.0 V)AN1406/D (105.0kB)2
ECL Clock Distribution TechniquesAN1405/D (54.0kB)1
ECLinPS Plus™ Spice Modeling KitAND8009/D (343.0kB)11
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information GuideAND8002 (71kB)12
Interfacing Between LVDS and ECLAN1568/D (121.0kB)11
Interfacing with ECLinPSAND8066/D (72kB)3
Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksAND8001/D (90.0kB)0
Storage and Handling of Drypack Surface Mount DeviceAND8003/D (49kB)2Mar, 2016
Termination of ECL Logic DevicesAND8020/D (176.0kB)6
The ECL Translator GuideAN1672/D (142.0kB)12
Thermal Analysis and Reliability of WIRE BONDED ECLAND8072/D (119.0kB)5
数据表 (1)
Document TitleDocument ID/SizeRevisionRevision Date
2.5V/3.3V 2:1:15 Differential ECL/PECL w/1 and w/2 Clock DriverNB100LVEP222/D (134kB)13
仿真模型 (2)
Document TitleDocument ID/SizeRevisionRevision Date
IBIS Model for nb100lvep222fa 2.5VNB100LVEP222FA_25.IBS (6.0kB)3
IBIS Model for nb100lvep222fa 3.3VNB100LVEP222FA_33.IBS (6.0kB)2
封装图纸 (2)
Document TitleDocument ID/SizeRevision
8X8MM 0.5MM PITCH485M (60.8kB)C
LQFP 52 LEAD EXPOSED PAD 10x10848H-01 (78.3kB)B
产品订购型号
产品状况Compliance封装MSL*容器预算价格 (1千个数量的单价)
NB100LVEP222FAGLast ShipmentsPb-free Halide freeLQFP-52848H-013Tray JEDEC160
NB100LVEP222FARGLast ShipmentsPb-free Halide freeLQFP-52848H-013Tape and Reel1500
NB100LVEP222MNGActivePb-free Halide freeQFN-52485M2Tray JEDEC260联系BDTIC
NB100LVEP222MNRGActivePb-free Halide freeQFN-52485M2Tape and Reel2000$7.95
订购产品技术参数
ProductTypeChannelsInput / Output RatioInput LevelOutput LevelVCC Typ (V)tJitterRMS Typ (ps)tskew(o-o) Max (ps)tpd Typ (ns)tR & tF Max (ps)fmaxClock Typ (MHz)fmaxData Typ (Mbps)
NB100LVEP222MNGBuffer12:1:15CML ECL LVDSECL3.3 2.51200.875 0.93001000
NB100LVEP222MNRGBuffer12:1:15ECL LVDS CMLECL3.3 2.51200.875 0.93001000
2.5V/3.3V 2:1:15 Differential ECL/PECL w/1 and w/2 Clock Driver (134kB) NB100LVEP222
AC Characteristics of ECL Devices NB100LVEP91
Clock Generation and Clock and Data Marking and Ordering Information Guide NB100LVEP91
Designing with PECL (ECL at +5.0 V) NB100LVEP91
ECL Clock Distribution Techniques NB100LVEP91
ECLinPS Plus™ Spice Modeling Kit MC10EPT20
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide NB100LVEP91
Interfacing Between LVDS and ECL NB100ELT23L
Interfacing with ECLinPS NB100LVEP91
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks NUP4201
Storage and Handling of Drypack Surface Mount Device NB3U23C
Termination of ECL Logic Devices NB100LVEP91
The ECL Translator Guide NB100LVEP91
Thermal Analysis and Reliability of WIRE BONDED ECL NB100LVEP91
IBIS Model for nb100lvep222fa 2.5V NB100LVEP222
IBIS Model for nb100lvep222fa 3.3V NB100LVEP222
LQFP 52 LEAD EXPOSED PAD 10x10 NB100LVEP222
8X8MM 0.5MM PITCH NB4L7210