NB3N502DEVB: PLL Clock Multiplier Evaluation Board

The NB3N502 Evaluation Board was designed to provide a flexible and convenient platform to quickly evaluate, characterize and verify the performance and operation of the NB3N502 PLL Clock Multiplier. The NB3N502 is a clock multiplier device that generates a low jitter, TTL/CMOS level output clock which is a precise multiple of the external input reference clock signal source. The user's manual provides detailed information on the board's contents, layout and use, and it should be used in conjunction with the NB3N502 data sheet which contains full technical details on device specifications and operation.

评估/开发工具信息
产品状况Compliance简短说明所用产品
NB3N502DEVBActivePLL Clock Multiplier Evaluation BoardNB3N502DG
NB3N502DR2G
技术文档
类型文档标题文档编号/大小修订号
Eval Board: ManualNB3N502DEVB Evaluation Board User's ManualEVBUM2064/D - 247.0 KB1
EVBUM2064/D - 247 NB3N502DEVB
NB3N502DEVB