NB7L11M: Clock / Data Fanout Buffer / Translator, 2.5 V / 3.3 V, with CML Outputs and Internal Termination

The NB7L11M is a differential 1-to-2 clock/data distribution chip with internal source termination and CML output structure, optimized for low skew and minimal jitter. The device produces two identical output copies of clock or data operating up to 8 GHz or 12 Gb/s, respectively.Inputs incorporate internal 50 Ohm termination resistors and accept NECL (Negative ECL), PECL (Positive ECL), CML, LVCMOS, LVTTL, or LVDS. Differential 16mA CML (Current Mode Logic) output provides matching 50 Ohm terminations, and 400 mV output swings when externally terminated, 50 Ohm to VCC.

特性

Maximum Input Clock up to 8 GHz Typical
Maximum Input Data Rate up to 12Gb/s Typical
< 0.5 ps of RMS Clock Jitter
< 10 ps of Data Dependent Jitter
30 ps Typical Rise and Fall Times
110 ps Typical Propogation Delay
3 ps Typical Within Device Skew
Operatiing Range: VCC = 2.375V to 3.465V with VEE = 0V
CML Output Level (400 mV Peak-to-Peak Output) Differential Output Only
50 Ω Internal Input and Output Termination Resistors
Functionally Compatible with Existing 2.5V / 3.3V LVEL,LVEP, EP, and SG DEvices
Pb-Free Packages are Available

应用

OC-48 & OC-192 SONET/SDH data routing
Serial Digital HDTV Video Routing
ATE High Speed Data Communications Links

应用注释 (14)

Document Title	Document ID/Size	Revision	Revision Date
AC Characteristics of ECL Devices	AND8090/D (896.0kB)	1
Board Mounting Notes for Quad Flat-Pack No-Lead Package (QFN)	AND8086/D (40.0kB)	0
Clock Generation and Clock and Data Marking and Ordering Information Guide	AND8002/D (71kB)	12
Designing with PECL (ECL at +5.0 V)	AN1406/D (105.0kB)	2
ECL Clock Distribution Techniques	AN1405/D (54.0kB)	1
ECLinPS, ECLinPS Lite, ECLinPS Plus and GigaComm Marking and Ordering Information Guide	AND8002 (71kB)	12
GigaComm (SiGe) SPICE Modeling Kit	AND8077/D (157kB)	6
Interfacing with ECLinPS	AND8066/D (72kB)	3
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks	AND8001/D (90.0kB)	0
Storage and Handling of Drypack Surface Mount Device	AND8003/D (49kB)	2	Mar, 2016
Termination and Interface of ON Semiconductor ECL Logic Devices with CML (Current Mode Logic) Output Structure	AND8173/D (144.0kB)	3
Termination of ECL Logic Devices	AND8020/D (176.0kB)	6
The ECL Translator Guide	AN1672/D (142.0kB)	12
Thermal Analysis and Reliability of WIRE BONDED ECL	AND8072/D (119.0kB)	5

数据表 (1)

Document Title	Document ID/Size	Revision	Revision Date
2.5 V / 3.3 V 12 Gb/s Differential 1:2 Clock/Data Fan-out Buffer/Translator with CML Outputs & Internal Termination Resistors	NB7L11M/D (223kB)	4	Aug, 2016