NBSG53A: 2.5 V / 3.3 V Selectable Differential Clock / Data D Flip-Flop / Clock Divider with Reset and OLS

The NBSG53A is a multi-function differential D flip-flop (DFF) or fixed divide by 2 (DIV/2) clock generator. This is part of the GigaComm family of high performance Silicon Germanium products. A strappable control pin is provided to select between the two functions. The device is housed in a low profile 4x4 mm 16-pin Flip-Chip BGA (FCBGA) package.The NBSG53A is a device with data, clock, OLS, reset, and select inputs. Differential inputs incorporate internal 50-ohm termination resistors and accept NECL (Negative ECL), PECL (Positive ECL), CMOS, CML, or LVDS. The OLS input is used to program the peak-to-peak output amplitude between 0 and 800 mV in five discrete steps. The RESET and SELECT inputs are single-ended and can be driven with either LVECL or LVCMOS input levels.Data is transferred to the outputs on the positive edge of the clock. The differential clock inputs of the NBSG53A allow the device to also be used as a negative edge triggered device.

特性
  • Maximum Input Clock Frequency (DFF) > 8 GHz Typical
  • Maximum Input Clock Frequency (DIV/2) > 10 GHz Typical
  • 210 ps Typical Propagation Delay (OLS = FLOAT)
  • 45 ps Typical Rise and Fall Times (OLS = FLOAT)
  • Selectable Output Level (0 V, 200 mV, 400 mV, 600 mV, or 800 mV Peak-to-Peak Output)
  • 50 Ω Internal Input Termination Resistors on all Differential Input
  • DIV/2 Mode (Active with Select Low)
  • D Flip Flop Mode (Active with Select High)
  • Selectable Swing PECL Output with Operating Range: VCC = 2.375 V to 3.465 V with VEE = 0 V
  • Selectable Swing NECL Output with NECL Inputs with Operating Range: VCC = 0 V with VEE = -2.375 V to -3.465 V
应用
  • High Performance Logic for ATE and Networking
终端产品
  • ATE Instrumentation, Networking
封装
应用注释 (13)
Document TitleDocument ID/SizeRevisionRevision Date
AC Characteristics of ECL DevicesAND8090/D (896.0kB)1
Board Mounting Considerations for FCBGA PackagesAND8075/D (56.0kB)0
Board Mounting Notes for Quad Flat-Pack No-Lead Package (QFN)AND8086/D (40.0kB)0
Chips that RipAND8068/D (25.0kB)0
Designing with PECL (ECL at +5.0 V)AN1406/D (105.0kB)2
ECL Clock Distribution TechniquesAN1405/D (54.0kB)1
Flip Chip CSP PackagesAND8081/D (261kB)2Mar, 2016
GigaComm (SiGe) SPICE Modeling KitAND8077/D (157kB)6
Interfacing with ECLinPSAND8066/D (72kB)3
Odd Number Divide By Counters with 50% Outputs and Synchronous ClocksAND8001/D (90.0kB)0
Storage and Handling of Drypack Surface Mount DeviceAND8003/D (49kB)2Mar, 2016
Termination of ECL Logic DevicesAND8020/D (176.0kB)6
Thermal Analysis and Reliability of WIRE BONDED ECLAND8072/D (119.0kB)5
数据表 (1)
Document TitleDocument ID/SizeRevisionRevision Date
2.5 V/3.3 V SiGe Selectable Differential Clock and Data D Flip-Flop/Clock Divider with Reset and OLSNBSG53A/D (162kB)15Jun, 2014
仿真模型 (9)
Document TitleDocument ID/SizeRevisionRevision Date
IBIS Model for nbsg53aba with all optionsNBSG53ABA.IBS (215.0kB)4
IBIS Model for nbsg53amn 2.5V 400mVNBSG53AMN_25_400.IBS (13.0kB)2
IBIS Model for nbsg53amn 2.5V 800mVNBSG53AMN_25_800.IBS (14.0kB)2
IBIS Model for nbsg53amn 3.3V 400mVNBSG53AMN_33_400.IBS (15.0kB)3
IBIS Model for nbsg53amn 3.3V 800mVNBSG53AMN_33_800.IBS (17.0kB)4
IBS Model for NBSG53ABA (2.5 V, 400 mV)NBSG53ABA_25V_400MV13.8.IBS (13.0kB)2
IBS Model for NBSG53ABA (2.5 V, 800 mV)NBSG53ABA_25V_800MV15.0.IBS (15.0kB)2
IBS Model for NBSG53ABA (3.3 V, 400 mV)NBSG53ABA_33V_400MV15.8.IBS (14.0kB)3
IBS Model for NBSG53ABA (3.3 V, 800mV)NBSG53ABA_33V_800MV18.0.IBS (17.0kB)2
封装图纸 (1)
Document TitleDocument ID/SizeRevision
QFN16, 3x3, 0.5P485G-01 (57.3kB)F
产品订购型号
产品状况Compliance封装MSL*容器预算价格 (1千个数量的单价)
NBSG53AMNGActivePb-free Halide freeQFN-16485G-011Tube123联系BDTIC
NBSG53AMNHTBGActivePb-free Halide freeQFN-16485G-011Tape and Reel100联系BDTIC
NBSG53AMNR2GActivePb-free Halide freeQFN-16485G-011Tape and Reel3000联系BDTIC
订购产品技术参数
ProductTypeBitsInput LevelOutput LevelVCC Typ (V)tJitter Typ (ps)tpd Typ (ns)tsu Min (ns)th Min (ns)trec Typ (ns)tR & tF Max (ps)fToggle Typ (MHz)
NBSG53AMNGD-Type1CMOS CML LVDS ECLECL2.5 3.30.50.2150.030.0250.0126510000
NBSG53AMNHTBGD-Type1LVDS CMOS ECL CMLECL2.5 3.30.50.2150.030.0250.0126510000
NBSG53AMNR2GD-Type1LVDS ECL CMOS CMLECL2.5 3.30.50.2150.030.0250.0126510000
2.5 V/3.3 V SiGe Selectable Differential Clock and Data D Flip-Flop/Clock Divider with Reset and OLS (162kB) NBSG53A
AC Characteristics of ECL Devices NB100LVEP91
Board Mounting Considerations for FCBGA Packages NBSG86A
Board Mounting Notes for Quad Flat-Pack No-Lead Package (QFN) NB100LVEP91
Chips that Rip NBSG86A
Designing with PECL (ECL at +5.0 V) NB100LVEP91
ECL Clock Distribution Techniques NB100LVEP91
Flip Chip CSP Packages N64S818HA
GigaComm (SiGe) SPICE Modeling Kit NBSG86A
Interfacing with ECLinPS NB100LVEP91
Odd Number Divide By Counters with 50% Outputs and Synchronous Clocks NUP4201
Storage and Handling of Drypack Surface Mount Device NB3U23C
Termination of ECL Logic Devices NB100LVEP91
Thermal Analysis and Reliability of WIRE BONDED ECL NB100LVEP91
IBIS Model for nbsg53aba with all options NBSG53A
IBIS Model for nbsg53amn 2.5V 400mV NBSG53A
IBIS Model for nbsg53amn 2.5V 800mV NBSG53A
IBIS Model for nbsg53amn 3.3V 400mV NBSG53A
IBIS Model for nbsg53amn 3.3V 800mV NBSG53A
IBS Model for NBSG53ABA (2.5 V, 400 mV) NBSG53A
IBS Model for NBSG53ABA (2.5 V, 800 mV) NBSG53A
IBS Model for NBSG53ABA (3.3 V, 400 mV) NBSG53A
IBS Model for NBSG53ABA (3.3 V, 800mV) NBSG53A
QFN16, 3x3, 0.5P NLSF308