EXTERNAL PORTS
These are the external ports defined in the MHS file.
Attributes Key The attributes are obtained from the SIGIS and IOB_STATE parameters set on the PORT in the MHS file CLK  indicates Clock ports, (SIGIS = CLK)  INTR  indicates Interrupt ports,(SIGIS = INTR)  RESET  indicates Reset ports, (SIGIS = RST)  BUF or REG  Indicates ports that instantiate or infer IOB primitives, (IOB_STATE = BUF or REG)
# NAME DIR [LSB:MSB] SIG ATTRIBUTES 0GLB fpga_0_SRAM_CLOCK O 1 sys_clk_s 1A fpga_0_DDR_SDRAM_64Mx32_DDR_DQS_pin IO 0:3 fpga_0_DDR_SDRAM_64Mx32_DDR_DQS 2A fpga_0_DDR_SDRAM_64Mx32_DDR_DQ_pin IO 0:31 fpga_0_DDR_SDRAM_64Mx32_DDR_DQ 3A fpga_0_DDR_SDRAM_64Mx32_DDR_Addr_pin O 0:12 fpga_0_DDR_SDRAM_64Mx32_DDR_Addr 4A fpga_0_DDR_SDRAM_64Mx32_DDR_BankAddr_pin O 0:1 fpga_0_DDR_SDRAM_64Mx32_DDR_BankAddr 5A fpga_0_DDR_SDRAM_64Mx32_DDR_CASn_pin O 1 fpga_0_DDR_SDRAM_64Mx32_DDR_CASn 6A fpga_0_DDR_SDRAM_64Mx32_DDR_CKE_pin O 1 fpga_0_DDR_SDRAM_64Mx32_DDR_CKE 7A fpga_0_DDR_SDRAM_64Mx32_DDR_CSn_pin O 1 fpga_0_DDR_SDRAM_64Mx32_DDR_CSn 8A fpga_0_DDR_SDRAM_64Mx32_DDR_Clk_pin O 1 fpga_0_DDR_SDRAM_64Mx32_DDR_Clk 9A fpga_0_DDR_SDRAM_64Mx32_DDR_Clkn_pin O 1 fpga_0_DDR_SDRAM_64Mx32_DDR_Clkn 10A fpga_0_DDR_SDRAM_64Mx32_DDR_DM_pin O 0:3 fpga_0_DDR_SDRAM_64Mx32_DDR_DM 11A fpga_0_DDR_SDRAM_64Mx32_DDR_RASn_pin O 1 fpga_0_DDR_SDRAM_64Mx32_DDR_RASn 12A fpga_0_DDR_SDRAM_64Mx32_DDR_WEn_pin O 1 fpga_0_DDR_SDRAM_64Mx32_DDR_WEn 13B fpga_0_Hard_Temac_0_GMII_RXD_0 I 0:7 fpga_0_Hard_Temac_0_GMII_RXD_0 14B fpga_0_Hard_Temac_0_GMII_RX_CLK_0 I 1 fpga_0_Hard_Temac_0_GMII_RX_CLK_0 15B fpga_0_Hard_Temac_0_GMII_RX_DV_0 I 1 fpga_0_Hard_Temac_0_GMII_RX_DV_0 16B fpga_0_Hard_Temac_0_GMII_RX_ER_0 I 1 fpga_0_Hard_Temac_0_GMII_RX_ER_0 17B fpga_0_Hard_Temac_0_MII_TX_CLK_0 I 1 fpga_0_Hard_Temac_0_MII_TX_CLK_0 18B fpga_0_Hard_Temac_0_MDIO_0_pin IO 1 fpga_0_Hard_Temac_0_MDIO_0				# NAME DIR [LSB:MSB] SIG ATTRIBUTES 19B fpga_0_Hard_Temac_0_GMII_TXD_0 O 0:7 fpga_0_Hard_Temac_0_GMII_TXD_0 20B fpga_0_Hard_Temac_0_GMII_TX_CLK_0 O 1 fpga_0_Hard_Temac_0_GMII_TX_CLK_0 21B fpga_0_Hard_Temac_0_GMII_TX_EN_0 O 1 fpga_0_Hard_Temac_0_GMII_TX_EN_0 22B fpga_0_Hard_Temac_0_GMII_TX_ER_0 O 1 fpga_0_Hard_Temac_0_GMII_TX_ER_0 23B fpga_0_Hard_Temac_0_MDC_0_pin O 1 fpga_0_Hard_Temac_0_MDC_0 24C fpga_0_RS232_Uart_RX_pin I 1 fpga_0_RS232_Uart_RX 25C fpga_0_RS232_Uart_TX_pin O 1 fpga_0_RS232_Uart_TX 26D fpga_0_SRAM_256Kx32_Mem_DQ_pin IO 0:31 fpga_0_SRAM_256Kx32_Mem_DQ 27D fpga_0_SRAM_256Kx32_Mem_ADV_LDN_pin O 1 fpga_0_SRAM_256Kx32_Mem_ADV_LDN 28D fpga_0_SRAM_256Kx32_Mem_BEN_pin O 0:3 fpga_0_SRAM_256Kx32_Mem_BEN 29D fpga_0_SRAM_256Kx32_Mem_OEN_pin O 0:0 fpga_0_SRAM_256Kx32_Mem_OEN 30D fpga_0_SRAM_256Kx32_Mem_WEN_pin O 1 fpga_0_SRAM_256Kx32_Mem_WEN 31E fpga_0_SRAM_256Kx32_Mem_A_pin O 9:29 fpga_0_SRAM_256Kx32_Mem_A 32F fpga_0_TriMode_MAC_GMII_PhyResetN_pin O 1 fpga_0_TriMode_MAC_GMII_PhyResetN 33G sys_clk_pin I 1 dcm_clk_s  CLK  34G fpga_0_SRAM_256Kx32_SRAM_CEN_pin O 1 net_gnd 35H fpga_0_DDR_CLK_FB I 1 ddr_feedback_s  CLK  36I sys_rst_pin I 1 sys_rst_s  RESET