$ Start of Compile #Sat Feb 19 07:22:58 2005 Synplicity VHDL Compiler, version Compilers 2.8.1, Build 050R, built Oct 6 2004 Copyright (C) 1994-2004, Synplicity Inc. All Rights Reserved VHDL syntax check successful! File E:\Projects\EmifTi\EMIF_V4\Vhdl\V4SmplFfsEmifC64x.vhd changed - recompiling Synthesizing work.v4smplffsemifc64x.v4smplffsemifc64x_arch @W:CD280 : v4smplffsemifc64x.vhd(88) | Unbound component IBUF_LVCMOS33 mapped to black box @W:CD280 : v4smplffsemifc64x.vhd(90) | Unbound component BUFIO mapped to black box @W:CD280 : v4smplffsemifc64x.vhd(91) | Unbound component BUFR mapped to black box Synthesizing work.bufr.syn_black_box Post processing for work.bufr.syn_black_box @W:CD280 : v4smplffsemifc64x.vhd(89) | Unbound component IOBUF_LVCMOS33 mapped to black box @W:CD280 : v4smplffsemifc64x.vhd(96) | Unbound component RAMB16_S4_S4 mapped to black box @W:CD280 : v4smplffsemifc64x.vhd(145) | Unbound component IBUFG mapped to black box @W:CD280 : v4smplffsemifc64x.vhd(116) | Unbound component DCM_BASE mapped to black box Synthesizing work.dcm_base.syn_black_box Post processing for work.dcm_base.syn_black_box @W:CD280 : v4smplffsemifc64x.vhd(146) | Unbound component BUFG mapped to black box @W:CD280 : v4smplffsemifc64x.vhd(147) | Unbound component FDP mapped to black box Synthesizing work.ibuf_lvcmos33.syn_black_box Post processing for work.ibuf_lvcmos33.syn_black_box Synthesizing work.iobuf_lvcmos33.syn_black_box Post processing for work.iobuf_lvcmos33.syn_black_box Synthesizing work.fdp.syn_black_box Post processing for work.fdp.syn_black_box Synthesizing work.bufg.syn_black_box Post processing for work.bufg.syn_black_box Synthesizing work.ibufg.syn_black_box Post processing for work.ibufg.syn_black_box Synthesizing work.ramb16_s4_s4.syn_black_box Post processing for work.ramb16_s4_s4.syn_black_box Synthesizing work.bufio.syn_black_box Post processing for work.bufio.syn_black_box Post processing for work.v4smplffsemifc64x.v4smplffsemifc64x_arch @W:CL159 : v4smplffsemifc64x.vhd(70) | Input dspsren is unused @END Process took 0h:0m:0s realtime, 0h:0m:0s cputime ###########################################################[ Synplicity Xilinx Technology Mapper, version 7.7.0, Build 054R, built Oct 6 2004 Copyright (C) 1994-2004, Synplicity Inc. All Rights Reserved Found 3 global buffers instantiated by user Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ ------------------------------------------------------------ Net buffering Report for view:work.V4SmplFfsEmifC64x(v4smplffsemifc64x_arch): No nets needed buffering. @N:FX164 : | The option to pack flops in the IOB has not been specified Writing Analyst data base E:\Projects\EmifTi\EMIF_V4\Synthesis\V4SmplFfsEmifC64x\rev_1\V4SmplFfsEmifC64x.srm Writing EDIF Netlist and constraint files Found clock V4SmplFfsEmifC64x|DspEclkOut with period 1000.00ns Found clock V4SmplFfsEmifC64x|intsysclk0tobufg_inferred_clock with period 1000.00ns Found clock V4SmplFfsEmifC64x|intclkdiv_inferred_clock with period 1000.00ns ##### START OF TIMING REPORT #####[ # Timing Report written on Sat Feb 19 07:23:02 2005 # Top view: V4SmplFfsEmifC64x Requested Frequency: 1.0 MHz Wire load mode: top Paths requested: 5 Constraint File(s): @N:MT195 : | This timing report estimates place and route data. Please look at the place and route timing report for final timing.. @N:MT196 : | Clock constraints cover all FF-to-FF, FF-to-output, input-to-FF and input-to-output paths associated with a particular clock.. Performance Summary ******************* Worst slack in design: 994.471 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ---------------------------------------------------------------------------------------------------------------------------------------------------------- V4SmplFfsEmifC64x|DspEclkOut 1.0 MHz 335.8 MHz 1000.000 2.978 997.022 inferred Inferred_clkgroup_2 V4SmplFfsEmifC64x|intclkdiv_inferred_clock 1.0 MHz 180.9 MHz 1000.000 5.529 994.471 inferred Inferred_clkgroup_0 V4SmplFfsEmifC64x|intsysclk0tobufg_inferred_clock 1.0 MHz 261.2 MHz 1000.000 3.829 996.171 inferred Inferred_clkgroup_1 System 1.0 MHz 191.0 MHz 1000.000 5.237 994.763 system default_clkgroup ========================================================================================================================================================== Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ V4SmplFfsEmifC64x|DspEclkOut V4SmplFfsEmifC64x|DspEclkOut | 1000.000 997.022 | No paths - | No paths - | No paths - V4SmplFfsEmifC64x|DspEclkOut V4SmplFfsEmifC64x|intclkdiv_inferred_clock | No paths - | No paths - | Diff grp - | No paths - V4SmplFfsEmifC64x|intsysclk0tobufg_inferred_clock V4SmplFfsEmifC64x|intsysclk0tobufg_inferred_clock | 1000.000 996.171 | No paths - | No paths - | No paths - V4SmplFfsEmifC64x|intclkdiv_inferred_clock V4SmplFfsEmifC64x|intclkdiv_inferred_clock | No paths - | 1000.000 994.471 | No paths - | No paths - ================================================================================================================================================================================================ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* Input Ports: Port Starting User Arrival Required Name Reference Constraint Time Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------- DspBEn[0] V4SmplFfsEmifC64x|DspEclkOut (rising) 0.000 0.000 997.022 997.022 DspBEn[1] V4SmplFfsEmifC64x|DspEclkOut (rising) 0.000 0.000 997.022 997.022 DspBEn[2] V4SmplFfsEmifC64x|DspEclkOut (rising) 0.000 0.000 997.022 997.022 DspBEn[3] V4SmplFfsEmifC64x|DspEclkOut (rising) 0.000 0.000 997.022 997.022 DspCEn V4SmplFfsEmifC64x|DspEclkOut (rising) 0.000 0.000 998.271 998.271 DspEA[0] V4SmplFfsEmifC64x|DspEclkOut (rising) 0.000 0.000 998.271 998.271 DspEA[1] V4SmplFfsEmifC64x|DspEclkOut (rising) 0.000 0.000 998.271 998.271 DspEA[2] V4SmplFfsEmifC64x|DspEclkOut (rising) 0.000 0.000 998.271 998.271 DspEA[3] V4SmplFfsEmifC64x|DspEclkOut (rising) 0.000 0.000 998.271 998.271 DspEA[4] V4SmplFfsEmifC64x|DspEclkOut (rising) 0.000 0.000 998.271 998.271 DspEA[5] V4SmplFfsEmifC64x|DspEclkOut (rising) 0.000 0.000 998.271 998.271 DspEA[6] V4SmplFfsEmifC64x|DspEclkOut (rising) 0.000 0.000 998.271 998.271 DspEA[7] V4SmplFfsEmifC64x|DspEclkOut (rising) 0.000 0.000 998.271 998.271 DspEA[8] V4SmplFfsEmifC64x|DspEclkOut (rising) 0.000 0.000 998.271 998.271 DspEA[9] V4SmplFfsEmifC64x|DspEclkOut (rising) 0.000 0.000 998.271 998.271 DspEA[10] V4SmplFfsEmifC64x|DspEclkOut (rising) 0.000 0.000 998.271 998.271 DspEA[11] V4SmplFfsEmifC64x|DspEclkOut (rising) 0.000 0.000 998.271 998.271 DspED[0] V4SmplFfsEmifC64x|DspEclkOut (rising) 0.000 0.000 998.271 998.271 DspED[1] V4SmplFfsEmifC64x|DspEclkOut (rising) 0.000 0.000 998.271 998.271 DspED[2] V4SmplFfsEmifC64x|DspEclkOut (rising) 0.000 0.000 998.271 998.271 DspED[3] V4SmplFfsEmifC64x|DspEclkOut (rising) 0.000 0.000 998.271 998.271 DspED[4] V4SmplFfsEmifC64x|DspEclkOut (rising) 0.000 0.000 998.271 998.271 DspED[5] V4SmplFfsEmifC64x|DspEclkOut (rising) 0.000 0.000 998.271 998.271 DspED[6] V4SmplFfsEmifC64x|DspEclkOut (rising) 0.000 0.000 998.271 998.271 DspED[7] V4SmplFfsEmifC64x|DspEclkOut (rising) 0.000 0.000 998.271 998.271 DspED[8] V4SmplFfsEmifC64x|DspEclkOut (rising) 0.000 0.000 998.271 998.271 DspED[9] V4SmplFfsEmifC64x|DspEclkOut (rising) 0.000 0.000 998.271 998.271 DspED[10] V4SmplFfsEmifC64x|DspEclkOut (rising) 0.000 0.000 998.271 998.271 DspED[11] V4SmplFfsEmifC64x|DspEclkOut (rising) 0.000 0.000 998.271 998.271 DspED[12] V4SmplFfsEmifC64x|DspEclkOut (rising) 0.000 0.000 998.271 998.271 DspED[13] V4SmplFfsEmifC64x|DspEclkOut (rising) 0.000 0.000 998.271 998.271 DspED[14] V4SmplFfsEmifC64x|DspEclkOut (rising) 0.000 0.000 998.271 998.271 DspED[15] V4SmplFfsEmifC64x|DspEclkOut (rising) 0.000 0.000 998.271 998.271 DspED[16] V4SmplFfsEmifC64x|DspEclkOut (rising) 0.000 0.000 998.271 998.271 DspED[17] V4SmplFfsEmifC64x|DspEclkOut (rising) 0.000 0.000 998.271 998.271 DspED[18] V4SmplFfsEmifC64x|DspEclkOut (rising) 0.000 0.000 998.271 998.271 DspED[19] V4SmplFfsEmifC64x|DspEclkOut (rising) 0.000 0.000 998.271 998.271 DspED[20] V4SmplFfsEmifC64x|DspEclkOut (rising) 0.000 0.000 998.271 998.271 DspED[21] V4SmplFfsEmifC64x|DspEclkOut (rising) 0.000 0.000 998.271 998.271 DspED[22] V4SmplFfsEmifC64x|DspEclkOut (rising) 0.000 0.000 998.271 998.271 DspED[23] V4SmplFfsEmifC64x|DspEclkOut (rising) 0.000 0.000 998.271 998.271 DspED[24] V4SmplFfsEmifC64x|DspEclkOut (rising) 0.000 0.000 998.271 998.271 DspED[25] V4SmplFfsEmifC64x|DspEclkOut (rising) 0.000 0.000 998.271 998.271 DspED[26] V4SmplFfsEmifC64x|DspEclkOut (rising) 0.000 0.000 998.271 998.271 DspED[27] V4SmplFfsEmifC64x|DspEclkOut (rising) 0.000 0.000 998.271 998.271 DspED[28] V4SmplFfsEmifC64x|DspEclkOut (rising) 0.000 0.000 998.271 998.271 DspED[29] V4SmplFfsEmifC64x|DspEclkOut (rising) 0.000 0.000 998.271 998.271 DspED[30] V4SmplFfsEmifC64x|DspEclkOut (rising) 0.000 0.000 998.271 998.271 DspED[31] V4SmplFfsEmifC64x|DspEclkOut (rising) 0.000 0.000 998.271 998.271 DspEclkOut NA NA NA NA NA DspSOEn System (rising) NA 0.000 994.800 994.800 DspSREn NA NA NA NA NA DspSWEn V4SmplFfsEmifC64x|DspEclkOut (rising) 0.000 0.000 998.271 998.271 FpgaClk NA NA NA NA NA Rst V4SmplFfsEmifC64x|intclkdiv_inferred_clock (falling) 0.000 0.000 997.632 997.632 SysAddr[0] V4SmplFfsEmifC64x|intsysclk0tobufg_inferred_clock (rising) 0.000 0.000 998.271 998.271 SysAddr[1] V4SmplFfsEmifC64x|intsysclk0tobufg_inferred_clock (rising) 0.000 0.000 998.271 998.271 SysAddr[2] V4SmplFfsEmifC64x|intsysclk0tobufg_inferred_clock (rising) 0.000 0.000 998.271 998.271 SysAddr[3] V4SmplFfsEmifC64x|intsysclk0tobufg_inferred_clock (rising) 0.000 0.000 998.271 998.271 SysAddr[4] V4SmplFfsEmifC64x|intsysclk0tobufg_inferred_clock (rising) 0.000 0.000 998.271 998.271 SysAddr[5] V4SmplFfsEmifC64x|intsysclk0tobufg_inferred_clock (rising) 0.000 0.000 998.271 998.271 SysAddr[6] V4SmplFfsEmifC64x|intsysclk0tobufg_inferred_clock (rising) 0.000 0.000 998.271 998.271 SysAddr[7] V4SmplFfsEmifC64x|intsysclk0tobufg_inferred_clock (rising) 0.000 0.000 998.271 998.271 SysAddr[8] V4SmplFfsEmifC64x|intsysclk0tobufg_inferred_clock (rising) 0.000 0.000 998.271 998.271 SysAddr[9] V4SmplFfsEmifC64x|intsysclk0tobufg_inferred_clock (rising) 0.000 0.000 998.271 998.271 SysAddr[10] V4SmplFfsEmifC64x|intsysclk0tobufg_inferred_clock (rising) 0.000 0.000 998.271 998.271 SysAddr[11] V4SmplFfsEmifC64x|intsysclk0tobufg_inferred_clock (rising) 0.000 0.000 998.271 998.271 SysDatIo[0] V4SmplFfsEmifC64x|intsysclk0tobufg_inferred_clock (rising) 0.000 0.000 998.271 998.271 SysDatIo[1] V4SmplFfsEmifC64x|intsysclk0tobufg_inferred_clock (rising) 0.000 0.000 998.271 998.271 SysDatIo[2] V4SmplFfsEmifC64x|intsysclk0tobufg_inferred_clock (rising) 0.000 0.000 998.271 998.271 SysDatIo[3] V4SmplFfsEmifC64x|intsysclk0tobufg_inferred_clock (rising) 0.000 0.000 998.271 998.271 SysDatIo[4] V4SmplFfsEmifC64x|intsysclk0tobufg_inferred_clock (rising) 0.000 0.000 998.271 998.271 SysDatIo[5] V4SmplFfsEmifC64x|intsysclk0tobufg_inferred_clock (rising) 0.000 0.000 998.271 998.271 SysDatIo[6] V4SmplFfsEmifC64x|intsysclk0tobufg_inferred_clock (rising) 0.000 0.000 998.271 998.271 SysDatIo[7] V4SmplFfsEmifC64x|intsysclk0tobufg_inferred_clock (rising) 0.000 0.000 998.271 998.271 SysDatIo[8] V4SmplFfsEmifC64x|intsysclk0tobufg_inferred_clock (rising) 0.000 0.000 998.271 998.271 SysDatIo[9] V4SmplFfsEmifC64x|intsysclk0tobufg_inferred_clock (rising) 0.000 0.000 998.271 998.271 SysDatIo[10] V4SmplFfsEmifC64x|intsysclk0tobufg_inferred_clock (rising) 0.000 0.000 998.271 998.271 SysDatIo[11] V4SmplFfsEmifC64x|intsysclk0tobufg_inferred_clock (rising) 0.000 0.000 998.271 998.271 SysDatIo[12] V4SmplFfsEmifC64x|intsysclk0tobufg_inferred_clock (rising) 0.000 0.000 998.271 998.271 SysDatIo[13] V4SmplFfsEmifC64x|intsysclk0tobufg_inferred_clock (rising) 0.000 0.000 998.271 998.271 SysDatIo[14] V4SmplFfsEmifC64x|intsysclk0tobufg_inferred_clock (rising) 0.000 0.000 998.271 998.271 SysDatIo[15] V4SmplFfsEmifC64x|intsysclk0tobufg_inferred_clock (rising) 0.000 0.000 998.271 998.271 SysDatIo[16] V4SmplFfsEmifC64x|intsysclk0tobufg_inferred_clock (rising) 0.000 0.000 998.271 998.271 SysDatIo[17] V4SmplFfsEmifC64x|intsysclk0tobufg_inferred_clock (rising) 0.000 0.000 998.271 998.271 SysDatIo[18] V4SmplFfsEmifC64x|intsysclk0tobufg_inferred_clock (rising) 0.000 0.000 998.271 998.271 SysDatIo[19] V4SmplFfsEmifC64x|intsysclk0tobufg_inferred_clock (rising) 0.000 0.000 998.271 998.271 SysDatIo[20] V4SmplFfsEmifC64x|intsysclk0tobufg_inferred_clock (rising) 0.000 0.000 998.271 998.271 SysDatIo[21] V4SmplFfsEmifC64x|intsysclk0tobufg_inferred_clock (rising) 0.000 0.000 998.271 998.271 SysDatIo[22] V4SmplFfsEmifC64x|intsysclk0tobufg_inferred_clock (rising) 0.000 0.000 998.271 998.271 SysDatIo[23] V4SmplFfsEmifC64x|intsysclk0tobufg_inferred_clock (rising) 0.000 0.000 998.271 998.271 SysDatIo[24] V4SmplFfsEmifC64x|intsysclk0tobufg_inferred_clock (rising) 0.000 0.000 998.271 998.271 SysDatIo[25] V4SmplFfsEmifC64x|intsysclk0tobufg_inferred_clock (rising) 0.000 0.000 998.271 998.271 SysDatIo[26] V4SmplFfsEmifC64x|intsysclk0tobufg_inferred_clock (rising) 0.000 0.000 998.271 998.271 SysDatIo[27] V4SmplFfsEmifC64x|intsysclk0tobufg_inferred_clock (rising) 0.000 0.000 998.271 998.271 SysDatIo[28] V4SmplFfsEmifC64x|intsysclk0tobufg_inferred_clock (rising) 0.000 0.000 998.271 998.271 SysDatIo[29] V4SmplFfsEmifC64x|intsysclk0tobufg_inferred_clock (rising) 0.000 0.000 998.271 998.271 SysDatIo[30] V4SmplFfsEmifC64x|intsysclk0tobufg_inferred_clock (rising) 0.000 0.000 998.271 998.271 SysDatIo[31] V4SmplFfsEmifC64x|intsysclk0tobufg_inferred_clock (rising) 0.000 0.000 998.271 998.271 SysEna V4SmplFfsEmifC64x|intsysclk0tobufg_inferred_clock (rising) 0.000 0.000 998.271 998.271 SysWre System (rising) NA 0.000 994.763 994.763 =============================================================================================================================== Output Ports: Port Starting User Arrival Required Name Reference Constraint Time Time Slack Clock ------------------------------------------------------------------------------------------------------------------------- DspED[0] V4SmplFfsEmifC64x|intclkdiv_inferred_clock (falling) NA 5.529 1000.000 994.471 DspED[1] V4SmplFfsEmifC64x|intclkdiv_inferred_clock (falling) NA 5.529 1000.000 994.471 DspED[2] V4SmplFfsEmifC64x|intclkdiv_inferred_clock (falling) NA 5.529 1000.000 994.471 DspED[3] V4SmplFfsEmifC64x|intclkdiv_inferred_clock (falling) NA 5.529 1000.000 994.471 DspED[4] V4SmplFfsEmifC64x|intclkdiv_inferred_clock (falling) NA 5.529 1000.000 994.471 DspED[5] V4SmplFfsEmifC64x|intclkdiv_inferred_clock (falling) NA 5.529 1000.000 994.471 DspED[6] V4SmplFfsEmifC64x|intclkdiv_inferred_clock (falling) NA 5.529 1000.000 994.471 DspED[7] V4SmplFfsEmifC64x|intclkdiv_inferred_clock (falling) NA 5.529 1000.000 994.471 DspED[8] V4SmplFfsEmifC64x|intclkdiv_inferred_clock (falling) NA 5.529 1000.000 994.471 DspED[9] V4SmplFfsEmifC64x|intclkdiv_inferred_clock (falling) NA 5.529 1000.000 994.471 DspED[10] V4SmplFfsEmifC64x|intclkdiv_inferred_clock (falling) NA 5.529 1000.000 994.471 DspED[11] V4SmplFfsEmifC64x|intclkdiv_inferred_clock (falling) NA 5.529 1000.000 994.471 DspED[12] V4SmplFfsEmifC64x|intclkdiv_inferred_clock (falling) NA 5.529 1000.000 994.471 DspED[13] V4SmplFfsEmifC64x|intclkdiv_inferred_clock (falling) NA 5.529 1000.000 994.471 DspED[14] V4SmplFfsEmifC64x|intclkdiv_inferred_clock (falling) NA 5.529 1000.000 994.471 DspED[15] V4SmplFfsEmifC64x|intclkdiv_inferred_clock (falling) NA 5.529 1000.000 994.471 DspED[16] V4SmplFfsEmifC64x|intclkdiv_inferred_clock (falling) NA 5.529 1000.000 994.471 DspED[17] V4SmplFfsEmifC64x|intclkdiv_inferred_clock (falling) NA 5.529 1000.000 994.471 DspED[18] V4SmplFfsEmifC64x|intclkdiv_inferred_clock (falling) NA 5.529 1000.000 994.471 DspED[19] V4SmplFfsEmifC64x|intclkdiv_inferred_clock (falling) NA 5.529 1000.000 994.471 DspED[20] V4SmplFfsEmifC64x|intclkdiv_inferred_clock (falling) NA 5.529 1000.000 994.471 DspED[21] V4SmplFfsEmifC64x|intclkdiv_inferred_clock (falling) NA 5.529 1000.000 994.471 DspED[22] V4SmplFfsEmifC64x|intclkdiv_inferred_clock (falling) NA 5.529 1000.000 994.471 DspED[23] V4SmplFfsEmifC64x|intclkdiv_inferred_clock (falling) NA 5.529 1000.000 994.471 DspED[24] V4SmplFfsEmifC64x|intclkdiv_inferred_clock (falling) NA 5.529 1000.000 994.471 DspED[25] V4SmplFfsEmifC64x|intclkdiv_inferred_clock (falling) NA 5.529 1000.000 994.471 DspED[26] V4SmplFfsEmifC64x|intclkdiv_inferred_clock (falling) NA 5.529 1000.000 994.471 DspED[27] V4SmplFfsEmifC64x|intclkdiv_inferred_clock (falling) NA 5.529 1000.000 994.471 DspED[28] V4SmplFfsEmifC64x|intclkdiv_inferred_clock (falling) NA 5.529 1000.000 994.471 DspED[29] V4SmplFfsEmifC64x|intclkdiv_inferred_clock (falling) NA 5.529 1000.000 994.471 DspED[30] V4SmplFfsEmifC64x|intclkdiv_inferred_clock (falling) NA 5.529 1000.000 994.471 DspED[31] V4SmplFfsEmifC64x|intclkdiv_inferred_clock (falling) NA 5.529 1000.000 994.471 SysDatIo[0] System (rising) NA 5.237 1000.000 994.763 SysDatIo[1] System (rising) NA 5.237 1000.000 994.763 SysDatIo[2] System (rising) NA 5.237 1000.000 994.763 SysDatIo[3] System (rising) NA 5.237 1000.000 994.763 SysDatIo[4] System (rising) NA 5.237 1000.000 994.763 SysDatIo[5] System (rising) NA 5.237 1000.000 994.763 SysDatIo[6] System (rising) NA 5.237 1000.000 994.763 SysDatIo[7] System (rising) NA 5.237 1000.000 994.763 SysDatIo[8] System (rising) NA 5.237 1000.000 994.763 SysDatIo[9] System (rising) NA 5.237 1000.000 994.763 SysDatIo[10] System (rising) NA 5.237 1000.000 994.763 SysDatIo[11] System (rising) NA 5.237 1000.000 994.763 SysDatIo[12] System (rising) NA 5.237 1000.000 994.763 SysDatIo[13] System (rising) NA 5.237 1000.000 994.763 SysDatIo[14] System (rising) NA 5.237 1000.000 994.763 SysDatIo[15] System (rising) NA 5.237 1000.000 994.763 SysDatIo[16] System (rising) NA 5.237 1000.000 994.763 SysDatIo[17] System (rising) NA 5.237 1000.000 994.763 SysDatIo[18] System (rising) NA 5.237 1000.000 994.763 SysDatIo[19] System (rising) NA 5.237 1000.000 994.763 SysDatIo[20] System (rising) NA 5.237 1000.000 994.763 SysDatIo[21] System (rising) NA 5.237 1000.000 994.763 SysDatIo[22] System (rising) NA 5.237 1000.000 994.763 SysDatIo[23] System (rising) NA 5.237 1000.000 994.763 SysDatIo[24] System (rising) NA 5.237 1000.000 994.763 SysDatIo[25] System (rising) NA 5.237 1000.000 994.763 SysDatIo[26] System (rising) NA 5.237 1000.000 994.763 SysDatIo[27] System (rising) NA 5.237 1000.000 994.763 SysDatIo[28] System (rising) NA 5.237 1000.000 994.763 SysDatIo[29] System (rising) NA 5.237 1000.000 994.763 SysDatIo[30] System (rising) NA 5.237 1000.000 994.763 SysDatIo[31] System (rising) NA 5.237 1000.000 994.763 ========================================================================================================================= ==================================== Detailed Report for Clock: V4SmplFfsEmifC64x|DspEclkOut ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------------- DspBEn[3:0] V4SmplFfsEmifC64x|DspEclkOut Port DspBEn[0] DspBEn[0] 0.000 997.022 DspBEn[3:0] V4SmplFfsEmifC64x|DspEclkOut Port DspBEn[1] DspBEn[1] 0.000 997.022 DspBEn[3:0] V4SmplFfsEmifC64x|DspEclkOut Port DspBEn[2] DspBEn[2] 0.000 997.022 DspBEn[3:0] V4SmplFfsEmifC64x|DspEclkOut Port DspBEn[3] DspBEn[3] 0.000 997.022 DspCEn V4SmplFfsEmifC64x|DspEclkOut Port DspCEn DspCEn 0.000 998.271 DspEA[11:0] V4SmplFfsEmifC64x|DspEclkOut Port DspEA[0] DspEA[0] 0.000 998.271 DspEA[11:0] V4SmplFfsEmifC64x|DspEclkOut Port DspEA[1] DspEA[1] 0.000 998.271 DspEA[11:0] V4SmplFfsEmifC64x|DspEclkOut Port DspEA[2] DspEA[2] 0.000 998.271 DspEA[11:0] V4SmplFfsEmifC64x|DspEclkOut Port DspEA[3] DspEA[3] 0.000 998.271 DspEA[11:0] V4SmplFfsEmifC64x|DspEclkOut Port DspEA[4] DspEA[4] 0.000 998.271 ========================================================================================================= Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------- intdatinbyten[0] V4SmplFfsEmifC64x|DspEclkOut FDCE CE intbyten_i[0] 999.397 997.022 intdatinbyten[1] V4SmplFfsEmifC64x|DspEclkOut FDCE CE intbyten_i[0] 999.397 997.022 intdatinbyten[2] V4SmplFfsEmifC64x|DspEclkOut FDCE CE intbyten_i[0] 999.397 997.022 intdatinbyten[3] V4SmplFfsEmifC64x|DspEclkOut FDCE CE intbyten_i[0] 999.397 997.022 intdatinbyten[4] V4SmplFfsEmifC64x|DspEclkOut FDCE CE intbyten_i[0] 999.397 997.022 intdatinbyten[5] V4SmplFfsEmifC64x|DspEclkOut FDCE CE intbyten_i[0] 999.397 997.022 intdatinbyten[6] V4SmplFfsEmifC64x|DspEclkOut FDCE CE intbyten_i[0] 999.397 997.022 intdatinbyten[7] V4SmplFfsEmifC64x|DspEclkOut FDCE CE intbyten_i[0] 999.397 997.022 intdatinbyten[8] V4SmplFfsEmifC64x|DspEclkOut FDCE CE intbyten_i[1] 999.397 997.022 intdatinbyten[9] V4SmplFfsEmifC64x|DspEclkOut FDCE CE intbyten_i[1] 999.397 997.022 ============================================================================================================= Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 1000.000 - Setup time: 0.603 = Required time: 999.397 - Propagation time: 2.375 = Slack (non-critical) : 997.022 Number of logic level(s): 2 Starting point: DspBEn[3:0] / DspBEn[0] Ending point: intdatinbyten[0] / CE The start point is clocked by V4SmplFfsEmifC64x|DspEclkOut [rising] The end point is clocked by V4SmplFfsEmifC64x|DspEclkOut [rising] on pin C Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------- DspBEn[3:0] Port DspBEn[0] In 0.000 0.000 - DspBEn[0] Net - - 0.000 - 0 TheEmifBytEn.0.EnBuf IBUF_LVCMOS33 I In - 0.000 - TheEmifBytEn.0.EnBuf IBUF_LVCMOS33 O Out 0.875 0.875 - intbyten[0] Net - - 0.522 - 1 TheEmifBytEn.0.intbyten_i[0] INV I In - 1.398 - TheEmifBytEn.0.intbyten_i[0] INV O Out 0.195 1.592 - intbyten_i[0] Net - - 0.783 - 8 intdatinbyten[0] FDCE CE In - 2.375 - ========================================================================================================= Total path delay (propagation time + setup) of 2.978 is 1.672(56.2%) logic and 1.306(43.8%) route. ==================================== Detailed Report for Clock: V4SmplFfsEmifC64x|intclkdiv_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------------------- GenRam.0.DspRam V4SmplFfsEmifC64x|intclkdiv_inferred_clock RAMB16_S4_S4 DOA[0] intdatout[0] 2.105 994.471 GenRam.0.DspRam V4SmplFfsEmifC64x|intclkdiv_inferred_clock RAMB16_S4_S4 DOA[1] intdatout[1] 2.105 994.471 GenRam.0.DspRam V4SmplFfsEmifC64x|intclkdiv_inferred_clock RAMB16_S4_S4 DOA[2] intdatout[2] 2.105 994.471 GenRam.0.DspRam V4SmplFfsEmifC64x|intclkdiv_inferred_clock RAMB16_S4_S4 DOA[3] intdatout[3] 2.105 994.471 GenRam.1.DspRam V4SmplFfsEmifC64x|intclkdiv_inferred_clock RAMB16_S4_S4 DOA[0] intdatout[4] 2.105 994.471 GenRam.1.DspRam V4SmplFfsEmifC64x|intclkdiv_inferred_clock RAMB16_S4_S4 DOA[1] intdatout[5] 2.105 994.471 GenRam.1.DspRam V4SmplFfsEmifC64x|intclkdiv_inferred_clock RAMB16_S4_S4 DOA[2] intdatout[6] 2.105 994.471 GenRam.1.DspRam V4SmplFfsEmifC64x|intclkdiv_inferred_clock RAMB16_S4_S4 DOA[3] intdatout[7] 2.105 994.471 GenRam.2.DspRam V4SmplFfsEmifC64x|intclkdiv_inferred_clock RAMB16_S4_S4 DOA[0] intdatout[8] 2.105 994.471 GenRam.2.DspRam V4SmplFfsEmifC64x|intclkdiv_inferred_clock RAMB16_S4_S4 DOA[1] intdatout[9] 2.105 994.471 =================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------------------------------------- DspED[31:0] V4SmplFfsEmifC64x|intclkdiv_inferred_clock Port DspED[0] DspED[0] 1000.000 994.471 DspED[31:0] V4SmplFfsEmifC64x|intclkdiv_inferred_clock Port DspED[1] DspED[1] 1000.000 994.471 DspED[31:0] V4SmplFfsEmifC64x|intclkdiv_inferred_clock Port DspED[2] DspED[2] 1000.000 994.471 DspED[31:0] V4SmplFfsEmifC64x|intclkdiv_inferred_clock Port DspED[3] DspED[3] 1000.000 994.471 DspED[31:0] V4SmplFfsEmifC64x|intclkdiv_inferred_clock Port DspED[4] DspED[4] 1000.000 994.471 DspED[31:0] V4SmplFfsEmifC64x|intclkdiv_inferred_clock Port DspED[5] DspED[5] 1000.000 994.471 DspED[31:0] V4SmplFfsEmifC64x|intclkdiv_inferred_clock Port DspED[6] DspED[6] 1000.000 994.471 DspED[31:0] V4SmplFfsEmifC64x|intclkdiv_inferred_clock Port DspED[7] DspED[7] 1000.000 994.471 DspED[31:0] V4SmplFfsEmifC64x|intclkdiv_inferred_clock Port DspED[8] DspED[8] 1000.000 994.471 DspED[31:0] V4SmplFfsEmifC64x|intclkdiv_inferred_clock Port DspED[9] DspED[9] 1000.000 994.471 ====================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 1000.000 = Required time: 1000.000 - Propagation time: 5.529 = Slack (critical) : 994.471 Number of logic level(s): 1 Starting point: GenRam.0.DspRam / DOA[0] Ending point: DspED[31:0] / DspED[0] The start point is clocked by V4SmplFfsEmifC64x|intclkdiv_inferred_clock [falling] on pin CLKA The end point is clocked by V4SmplFfsEmifC64x|intclkdiv_inferred_clock [falling] Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------- GenRam.0.DspRam RAMB16_S4_S4 DOA[0] Out 2.105 2.105 - intdatout[0] Net - - 0.522 - 1 TheEmifDat.0.IoBuf IOBUF_LVCMOS33 I In - 2.627 - TheEmifDat.0.IoBuf IOBUF_LVCMOS33 IO Out 2.901 5.529 - DspED[0] Net - - 0.000 - 0 DspED[31:0] Port DspED[0] Out - 5.529 - =============================================================================================== Total path delay (propagation time + setup) of 5.529 is 5.006(90.5%) logic and 0.522(9.5%) route. ==================================== Detailed Report for Clock: V4SmplFfsEmifC64x|intsysclk0tobufg_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------------------------------------------------------- intsysdatoutff2[0] V4SmplFfsEmifC64x|intsysclk0tobufg_inferred_clock FDC Q intsysdatoutff2[0] 0.348 996.171 intsysdatoutff2[1] V4SmplFfsEmifC64x|intsysclk0tobufg_inferred_clock FDC Q intsysdatoutff2[1] 0.348 996.171 intsysdatoutff2[2] V4SmplFfsEmifC64x|intsysclk0tobufg_inferred_clock FDC Q intsysdatoutff2[2] 0.348 996.171 intsysdatoutff2[3] V4SmplFfsEmifC64x|intsysclk0tobufg_inferred_clock FDC Q intsysdatoutff2[3] 0.348 996.171 intsysdatoutff2[4] V4SmplFfsEmifC64x|intsysclk0tobufg_inferred_clock FDC Q intsysdatoutff2[4] 0.348 996.171 intsysdatoutff2[5] V4SmplFfsEmifC64x|intsysclk0tobufg_inferred_clock FDC Q intsysdatoutff2[5] 0.348 996.171 intsysdatoutff2[6] V4SmplFfsEmifC64x|intsysclk0tobufg_inferred_clock FDC Q intsysdatoutff2[6] 0.348 996.171 intsysdatoutff2[7] V4SmplFfsEmifC64x|intsysclk0tobufg_inferred_clock FDC Q intsysdatoutff2[7] 0.348 996.171 intsysdatoutff2[8] V4SmplFfsEmifC64x|intsysclk0tobufg_inferred_clock FDC Q intsysdatoutff2[8] 0.348 996.171 intsysdatoutff2[9] V4SmplFfsEmifC64x|intsysclk0tobufg_inferred_clock FDC Q intsysdatoutff2[9] 0.348 996.171 ======================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------------------------------- SysDatIo[31:0] V4SmplFfsEmifC64x|intsysclk0tobufg_inferred_clock Port SysDatIo[0] SysDatIo[0] 1000.000 996.171 SysDatIo[31:0] V4SmplFfsEmifC64x|intsysclk0tobufg_inferred_clock Port SysDatIo[1] SysDatIo[1] 1000.000 996.171 SysDatIo[31:0] V4SmplFfsEmifC64x|intsysclk0tobufg_inferred_clock Port SysDatIo[2] SysDatIo[2] 1000.000 996.171 SysDatIo[31:0] V4SmplFfsEmifC64x|intsysclk0tobufg_inferred_clock Port SysDatIo[3] SysDatIo[3] 1000.000 996.171 SysDatIo[31:0] V4SmplFfsEmifC64x|intsysclk0tobufg_inferred_clock Port SysDatIo[4] SysDatIo[4] 1000.000 996.171 SysDatIo[31:0] V4SmplFfsEmifC64x|intsysclk0tobufg_inferred_clock Port SysDatIo[5] SysDatIo[5] 1000.000 996.171 SysDatIo[31:0] V4SmplFfsEmifC64x|intsysclk0tobufg_inferred_clock Port SysDatIo[6] SysDatIo[6] 1000.000 996.171 SysDatIo[31:0] V4SmplFfsEmifC64x|intsysclk0tobufg_inferred_clock Port SysDatIo[7] SysDatIo[7] 1000.000 996.171 SysDatIo[31:0] V4SmplFfsEmifC64x|intsysclk0tobufg_inferred_clock Port SysDatIo[8] SysDatIo[8] 1000.000 996.171 SysDatIo[31:0] V4SmplFfsEmifC64x|intsysclk0tobufg_inferred_clock Port SysDatIo[9] SysDatIo[9] 1000.000 996.171 ====================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 1000.000 = Required time: 1000.000 - Propagation time: 3.829 = Slack (non-critical) : 996.171 Number of logic level(s): 1 Starting point: intsysdatoutff2[0] / Q Ending point: SysDatIo[31:0] / SysDatIo[0] The start point is clocked by V4SmplFfsEmifC64x|intsysclk0tobufg_inferred_clock [rising] on pin C The end point is clocked by V4SmplFfsEmifC64x|intsysclk0tobufg_inferred_clock [rising] Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------- intsysdatoutff2[0] FDC Q Out 0.348 0.348 - intsysdatoutff2[0] Net - - 0.580 - 1 TheSysDat.0.SysIoBuf IOBUF_LVCMOS33 I In - 0.928 - TheSysDat.0.SysIoBuf IOBUF_LVCMOS33 IO Out 2.901 3.829 - SysDatIo[0] Net - - 0.000 - 0 SysDatIo[31:0] Port SysDatIo[0] Out - 3.829 - ==================================================================================================== Total path delay (propagation time + setup) of 3.829 is 3.249(84.9%) logic and 0.580(15.1%) route. ==================================== Detailed Report for Clock: System ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------- SysWre System Port SysWre SysWre 0.000 994.763 DspSOEn System Port DspSOEn DspSOEn 0.000 994.800 =============================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------------- SysDatIo[31:0] System Port SysDatIo[0] SysDatIo[0] 1000.000 994.763 SysDatIo[31:0] System Port SysDatIo[1] SysDatIo[1] 1000.000 994.763 SysDatIo[31:0] System Port SysDatIo[2] SysDatIo[2] 1000.000 994.763 SysDatIo[31:0] System Port SysDatIo[3] SysDatIo[3] 1000.000 994.763 SysDatIo[31:0] System Port SysDatIo[4] SysDatIo[4] 1000.000 994.763 SysDatIo[31:0] System Port SysDatIo[5] SysDatIo[5] 1000.000 994.763 SysDatIo[31:0] System Port SysDatIo[6] SysDatIo[6] 1000.000 994.763 SysDatIo[31:0] System Port SysDatIo[7] SysDatIo[7] 1000.000 994.763 SysDatIo[31:0] System Port SysDatIo[8] SysDatIo[8] 1000.000 994.763 SysDatIo[31:0] System Port SysDatIo[9] SysDatIo[9] 1000.000 994.763 ============================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 1000.000 = Required time: 1000.000 - Propagation time: 5.237 = Slack (non-critical) : 994.763 Number of logic level(s): 3 Starting point: SysWre / SysWre Ending point: SysDatIo[31:0] / SysDatIo[0] The start point is clocked by System [rising] The end point is clocked by System [rising] Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------- SysWre Port SysWre In 0.000 0.000 - SysWre Net - - 0.000 - 0 SysWrBuf IBUF_LVCMOS33 I In - 0.000 - SysWrBuf IBUF_LVCMOS33 O Out 0.875 0.875 - intsyswreff2 Net - - 0.559 - 2 intsyswreff2_i INV I In - 1.434 - intsyswreff2_i INV O Out 0.195 1.628 - intsyswreff2_i Net - - 0.707 - 32 TheSysDat.0.SysIoBuf IOBUF_LVCMOS33 T In - 2.336 - TheSysDat.0.SysIoBuf IOBUF_LVCMOS33 IO Out 2.901 5.237 - SysDatIo[0] Net - - 0.000 - 0 SysDatIo[31:0] Port SysDatIo[0] Out - 5.237 - ==================================================================================================== Total path delay (propagation time + setup) of 5.237 is 3.970(75.8%) logic and 1.266(24.2%) route. ##### END OF TIMING REPORT #####] --------------------------------------- Resource Usage Report for V4SmplFfsEmifC64x Mapping to part: xc4vlx25ff668-10 Cell usage: BUFIO 1 use BUFR 1 use DCM_BASE 1 use FDC 170 uses FDCE 32 uses FDP 1 use GND 1 use RAMB16_S4_S4 8 uses I/O primitives: 100 IBUFG 1 use IBUF_LVCMOS33 35 uses IOBUF_LVCMOS33 64 uses BUFG 1 use I/O Register bits: 0 Register bits not including I/Os: 203 (0%) RAM/ROM usage summary Block Rams : 8 of 72 (11%) Global Clock Buffers: 1 of 32 (3%) Mapping Summary: Total LUTs: 0 (0%) Mapper successful! Process took 0h:0m:1s realtime, 0h:0m:1s cputime ###########################################################]