Doc ID: DOC-1560
Change
Table 1-1 Clock Sources and Dividers contains incorrect information. For correct information, see the processor data sheet.
Doc ID: DOC-1600
Change
The One Time Programmable Memory Controller (OTPC) and Static Memory Controller (SMC) sections are incorrect. For the correct information, see the processor data sheet.
Doc ID: DOC-1599
Change
Table 1-4 and Table 1-5 SYS_BMODE Selections and Boot Modes, are incorrect. For correct information, see the processor data sheet.
Doc ID: DOC-1552
Change
In table 12-1 (ADSP-BF70x OTP Layout), the value for bootModeDisable is not correct.
Change from: bootModeDisable = 0x343 + 24 - 0x343
Change to: bootModeDisable = 0x30 + 24 - 0x343
Doc ID: DOC-1553
Change
In table 12-1 (ADSP-BF70x OTP Layout), the fsn (factoryserialnumber) field does not appear. Add the the following row to the table for this field.
| Name | Byte Address | Size (bits) | Description |
|---|---|---|---|
| fsn | 0x380 + 0 - 0x38c | 128 | Factory serial number |
Doc ID: DOC-1572
Change
Table 16-5 (PDF page 675) is not correct. Change from
"EXTCLK: Counts “clock ticks” from the system clock (SCLK) or an externally applied waveform."
Change to:
"EXTCLK: Counts edges of an externally applied waveform."
Doc ID: DOC-1580
Change
Wakeup from Deep Sleep State
To conserve power when the chip is idle, systems often uses powerdown modes to either shut down the clocks to various parts of the chip and/or power. In Deep Sleep state, core will be idle and the power dissipation on the VDD_INT power domain is reduced by gating all the core and system clocks and by disabling the PLL.
An USB event (active high polarity only) can take the processor out of Deep Sleep. In order to retain the USB communication after exiting deep sleep, the PHY must be configured appropriately to retain the state of D+/D-, thus avoiding the need to re-enumerate. The below condition has to be satisfied from the USB PHY.
Before entering deep sleep, set the HIBER bit (set to 1) and clear the RESTORE bit (set to 0) in the PHY Control register. This is usually done in the USB suspend handler.
After exiting deep sleep, clear the HIBER bit (set to 0) and set the RESTORE bit (set to 1) in the PHY Control register. This is usually done in the DPM Event handler.
main()
{
/* Set up USB as a wakeup event. Active high polarity only */
*pREG_DPM0_WAKE_POL = BITM_DPM_WAKE_POL_WS5;
*pREG_DPM0_WAKE_EN = BITM_DPM_WAKE_EN_WS5;
}
USB_SUSPEND_HANDLER()
{
/* Set HIBER bit and CLEAR RESTORE bit */
*pREG_USB0_PHY_CTL |= BITM_USB_PHY_CTL_HIBBER;
*pREG_USB0_PHY_CTL &= ~(BITM_USB_PHY_CTL_RESTORE);
/* Enter DeepSleep mode */
}
DPM0_EVT_Int_Handler() /* this is invoked when the processor comes out of Deep Sleep */
{
/* Clear the HIBER bit and Set the RESTORE bit */
*pREG_USB0_PHY_CTL &= ~(BITM_USB_PHY_CTL_HIBER);
*pREG_USB0_PHY_CTL |= BITM_USB_PHY_CTL_RESTORE;
}
Doc ID: DOC-1550
Change
There is a bit description missing in table 22-75, USB_PHY_CTL Register Fields. This is bit 4 (DIS) which has the following description.
DIS, Disable PHY
0 - USB PHY and 5V protection on USB signals enabled.
1 - USB PHY and 5V protection on USB signals disabled. Disabling the PHY and 5V protection results in reduced hibernate current.CAUTION- With 5V protection disabled the absolute max voltage on USB signals is reduced. See the data sheet for details.
Doc ID: DOC-1555
Change
Figure 36-6: SPI Memory Connections is incorrect in that it does not show memory-mapped boot and it shows SPI0 where it should show SPI2.
Additionally, every resistor shown in the SPI Memory Connections figure should be 10 kohm instead of 10 ohm.
Doc ID: DOC-1557
Change
Figure 36-20 (dBootCommand for SPI Master Boot) is the Incorrect Version. Contact processor.tools.support@analog.com for correct version.
Last Update Date: Oct 23 2014
