AD6642 Dual IF Receiver

The AD6642 is an 11-bit, 200 MSPS, dual-channel intermediate frequency (IF) receiver specifically designed to support multi-antenna systems in telecommunication applications where high dynamic range performance, low power, and small size are desired.

The device consists of two high performance analog-to-digital converters (ADCs) and noise shaping requantizer (NSR) digital blocks. Each ADC consists of a multistage, differential pipelined architecture with integrated output error correction logic. The ADC features a wide bandwidth switched-capacitor sampling network within the first stage of the differential pipeline. An integrated voltage reference eases design considerations. A duty cycle stabilizer (DCS) compensates for variations in the ADC clock duty cycle, allowing the converters to maintain excellent performance.

Each ADC output is connected internally to an NSR block. The integrated NSR circuitry allows for improved SNR performance in a smaller frequency band within the Nyquist bandwidth. The device supports two different output modes selectable via the external MODE pin or the SPI.

With the NSR feature enabled, the outputs of the ADCs are processed such that the AD6642 supports enhanced SNR performance within a limited portion of the Nyquist bandwidth while maintaining an 11-bit output resolution. The NSR block can be programmed to provide a bandwidth of either 22% or 33% of the sample clock. For example, with a sample clock rate of 185 MSPS, the AD6642 can achieve up to 75.5 dBFS SNR for a 40 MHz bandwidth in the 22% mode and up to 73.7 dBFS SNR for a 60 MHz bandwidth in the 33% mode.

With the NSR block disabled, the ADC data is provided directly to the output with a resolution of 11 bits. The AD6642 can achieve up to 66.5 dBFS SNR for the entire Nyquist bandwidth when operated in this mode. This allows the AD6642 to be used in telecommunication applications such as a digital predistortion observation path where wider bandwidths are desired.

After digital signal processing, multiplexed output data is routed into two 11-bit output ports such that the maximum data rate is 400 Mbps (DDR). These outputs are set at 1.8 V LVDS and support ANSI-644 levels. The AD6642 receiver digitizes a wide spectrum of IF frequencies. Each receiver is designed for simultaneous reception of a separate antenna. This IF sampling architecture greatly reduces compo-nent cost and complexity compared with traditional analog techniques or less integrated digital methods.

Flexible power-down options allow significant power savings. Programming for device setup and control is accomplished using a 3-wire SPI-compatible serial interface with numerous modes to support board-level system testing. The AD6642 is available in a Pb-free/RoHS compliant, 144-ball, 10 mm × 10 mm chip scale package ball grid array (CSP_BGA) and is specified over the industrial temperature range of −40°C to +85°C.

Applications
  • Communications
  • Diversity radio and smart antenna (MIMO) systems
  • Multimode digital receivers (3G)
  • WCDMA, LTE, CDMA2000
  • WiMAX, TD-SCDMA
  • I/Q demodulation systems
  • General-purpose software radios
Features and Benefits
  • 11-bit, 200 MSPS output data rate per channel
  • Integrated noise shaping requantizer (NSR)
  • Performance with NSR enabled
    SNR: 75.5 dBFS in 40 MHz band to 70 MHz @ 185 MSPS
    SNR: 73.7 dBFS in 60 MHz band to 70 MHz @ 185 MSPS
  • Performance with NSR disabled
    SNR: 66.5 dBFS to 70 MHz @ 185 MSPS
    SFDR: 83 dBc to 70 MHz @ 185 MSPS
  • Low power: 0.62 W @ 185 MSPS
  • 1.8 V analog supply operation
  • 1.8 V LVDS (ANSI-644 levels) output
  • 1-to-8 integer clock divider
  • Internal ADC voltage reference
  • 1.75 V p-p analog input range
    (programmable to 2.0 V p-p)
  • Differential analog inputs with 800 MHz bandwidth
  • See data sheet for additional features
RF & Microwave
Communications
    Data Sheets
    Documentnote
    AD6642: Dual IF Receiver Data Sheet (Rev. A)PDF 1147 kB
    Application Notes
    Documentnote
    AN-878: High Speed ADC SPI Control Software (Rev. A)PDF 585 kB
    AN-905: Visual Analog Converter Evaluation Tool Version 1.0 User Manual (Rev. 0)PDF 2124 kB
    AN-835: Understanding High Speed ADC Testing and Evaluation (Rev. B)PDF 985 kB
    AN-501: Aperture Uncertainty and ADC System Performance (Rev. A)PDF 227 kB
    AN-282: Fundamentals of Sampled Data SystemsPDF 2131 kB
    AN-756: Sampled Systems and the Effects of Clock Phase Noise and Jitter (Rev. 0)PDF 291.7 K
    AN-827: A Resonant Approach to Interfacing Amplifiers to Switched-Capacitor ADCs (Rev. 0)PDF 203 kB
    AN-935: Designing an ADC Transformer-Coupled Front End (Rev. 0)PDF 363 kB
    AN-742: Frequency Domain Response of Switched-Capacitor ADCs (Rev. B)PDF 401 kB
    AN-345: Grounding for Low-and-High-Frequency CircuitsPDF 455 kB
    AN-586: LVDS Outputs for High Speed A/D Converters (Rev. 0)PDF 207 kB
    AN-1142: Techniques for High Speed ADC PCB Layout (Rev. 0)PDF 392 kB
    AN-737: How ADIsimADC Models an ADC (Rev. B)PDF 373 kB
    AN-807: Multicarrier WCDMA Feasibility (Rev. 0)PDF 969 kB
    AN-808: Multicarrier CDMA2000 Feasibility (Rev. 0)PDF 1535 kB
    AN-851: A WiMax Double Downconversion IF Sampling Receiver Design (Rev. 0)PDF 262 kB
    AN-741: Little Known Characteristics of Phase Noise (Rev. 0)PDF 1679 kB
    User Guides
    Documentnote
    UG-232: Evaluating the AD6642/AD6657 Analog-to-Digital ConvertersPDF 2466 kB
    Order Information
    Part NumberPackagePacking QtyTemp RangePrice 100-499Price 1000+RoHS
    AD6642BBCZ Production144 ball CSPBGA (10x10x1.4mm)OTH 184-40 to 85C86.6373.64Y
    Evaluation Boards
    Part NumberDescriptionPriceRoHS
    AD6642EBZEvaluation Board300Y
    AD6642: Dual IF Receiver Data Sheet (Rev. A) ad6642
    AN-878: High Speed ADC SPI Control Software (Rev. A) ad6655
    AN-905: Visual Analog Converter Evaluation Tool Version 1.0 User Manual (Rev. 0) ad9220
    AN-835: Understanding High Speed ADC Testing and Evaluation (Rev. B) ad9220
    AN-501: Aperture Uncertainty and ADC System Performance (Rev. A) ad9220
    AN-282: Fundamentals of Sampled Data Systems ad1674
    AN-756: Sampled Systems and the Effects of Clock Phase Noise and Jitter (Rev. 0) ad9220
    AN-827: A Resonant Approach to Interfacing Amplifiers to Switched-Capacitor ADCs (Rev. 0) ad6655
    AN-935: Designing an ADC Transformer-Coupled Front End (Rev. 0) ad9220
    AN-742: Frequency Domain Response of Switched-Capacitor ADCs (Rev. B) ad7476
    AN-345: Grounding for Low-and-High-Frequency Circuits ad9220
    AN-586: LVDS Outputs for High Speed A/D Converters (Rev. 0) ad6642
    AN-835: 高速ADC测试和评估 (Rev. 0) ad9510
    AN-1142: 高速ADC PCB布局布线技巧 (Rev. 0) ad6655
    AN-1142: Techniques for High Speed ADC PCB Layout (Rev. 0) ad6655
    AN-878: 高速ADC SPI控制软件[中文版] (Rev. A) ad6655
    AN-282: 采样数据系统基本原理[中文版] (Rev. A) ad75019
    AN-737: 如何用ADIsimADC完成ADC建模 (Rev. B) ad6642
    AN-737: How ADIsimADC Models an ADC (Rev. B) ad9220
    AN-807: 多载波WCDMA的可行性 (Rev. 0) adf4106
    AN-807: Multicarrier WCDMA Feasibility (Rev. 0) ad6655
    AN-808: Multicarrier CDMA2000 Feasibility (Rev. 0) ad9863
    AN-827: 放大器与开关电容ADC接口的匹配方法[中文版] (Rev. 0) ad8351
    AN-905: VisualAnalog™转换器评估工具1.0版用户手册 (Rev. 0) ad6655
    AN-935: ADC变压器耦合前端设计[中文版] (Rev. 0) ad6655
    AN-586: 高速模数转换器的LVDS数据输出[中文版] (Rev. 0) ad6642
    AN-851: 一种WiMax双下变频IF采样接收机设计方案[中文版] (Rev. 0) ad9540
    AN-851: A WiMax Double Downconversion IF Sampling Receiver Design (Rev. 0) ad9856
    AN-345: 低频和高频电路接地 ad9540
    AN-756: 系统采样以及时钟相位噪声和抖动的影响[中文版] (Rev. 0) ad9540
    AN-501: 孔径不确定度与ADC系统性能[中文版] (Rev. A) ad9540
    AN-741: Little Known Characteristics of Phase Noise (Rev. 0) ad9221
    AN-741: 鲜为人知的相位噪声特性 ad9540
    UG-232: Evaluating the AD6642/AD6657 Analog-to-Digital Converters ad6642
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