AD6676 Wideband IF Receiver Subsystem _ BDTIC a Leading Distributor in China

AD6676 Wideband IF Receiver Subsystem

For a limited time, take a live test drive of the AD6676 by using our remote evaluation software.

The AD6676 is a highly integrated IF subsystem that can digitize radio frequency (RF) bands up to 160 MHz in width centered on an intermediate frequency (IF) of 70 MHz to 450 MHz. Unlike traditional Nyquist IF sampling ADCs, the AD6676 relies on a tunable band-pass Σ-Δ ADC with a high oversampling ratio to eliminate the need for band specific IF SAW filters and gain stages, resulting in significant simplification of the wideband radio receiver architecture. On-chip quadrature digital downconversion followed by selectable decimation filters reduces the complex data rate to a manageable rate between 62.5 MSPS to 266.7 MSPS. The 16-bit complex output data is transferred to the host via a single or dual lane JESD204B interface supporting line rates of up to 5.333 Gbps.

Applications

Features and Benefits

High instantaneous dynamic range

Noise figure (NF) as low as 13 dB
Noise spectral density (NSD) as low as −159 dBFS/Hz
IIP3 up to 36.9 dBm with spurious tones <−99 dBFS

Noise figure (NF) as low as 13 dB

Noise spectral density (NSD) as low as −159 dBFS/Hz

IIP3 up to 36.9 dBm with spurious tones <−99 dBFS

Tunable band-pass Σ-Δ analog-to-digital converter (ADC)

20 MHz to 160 MHz signal bandwidth
70 MHz to 450 MHz IF center frequency
Configurable input full-scale level of −2 dBm to −14 dBm – Easy to drive resistive IF input
Gain flatness of 1 dB with under 0.5 dB out-of-band peaking
Alias rejection greater than 50 dB
2.0 GSPS to 3.2 GSPS ADC clock rate – On-chip PLL clock multiplier
16-bit I/Q rate up to 266 MSPS

20 MHz to 160 MHz signal bandwidth

70 MHz to 450 MHz IF center frequency

Configurable input full-scale level of −2 dBm to −14 dBm
– Easy to drive resistive IF input

Gain flatness of 1 dB with under 0.5 dB out-of-band peaking

Alias rejection greater than 50 dB

2.0 GSPS to 3.2 GSPS ADC clock rate
– On-chip PLL clock multiplier

16-bit I/Q rate up to 266 MSPS

On-chip digital signal processing

NCO and quadrature digital downconverter (QDDC)
Selectable decimation factor of 12, 16, 24, and 32

NCO and quadrature digital downconverter (QDDC)

Selectable decimation factor of 12, 16, 24, and 32

See data sheet for additional features

RF & Microwave

IF/RF Receivers

Communications

Aerospace and Defense

Solutions

Data Sheets

Document	note
AD6676: Wideband IF Receiver Subsystem Data Sheet (Rev. B)	PDF 1.92 M

User Guides

Document	note
AD6676: Design Tools And Startup Guide For The Ad6676 Evaluation Board, A High Dynamic Range, Wideband Receiver	WIKI

Order Information

Part Number	Package	Packing Qty	Temp Range	Price 100-499	Price 1000+	RoHS
AD6676BCBZRL Production	80 ball WLCSP (4.29x5.04mm)	REEL 2000	-40 to 85C	170.58	145	Y

Evaluation Boards

Part Number	Description	Price	RoHS
AD6676EBZ	Evaluation Board	395	Y

Reference Materials

Technical Articles：MS-2739: High Dynamic IF Receiver Simplifies Design of Next Generation µW...
Technical Articles：A Wideband Analog Front End Based on a Continuous Time, ∆-Σ High Speed ADC...
FPGA Interoperability Reports：Altera AN-753 (AD6676 Arria 10)

AD6676: Wideband IF Receiver Subsystem Data Sheet (Rev. B) ad6676

MS-2739: 高动态范围IF接收器可简化新一代W点对点调制解调器的设计 adl5246

A Wideband Analog Front End Based on a Continuous Time, ∆-Σ High Speed ADC... ad6676

Altera AN-753 (AD6676 Arria 10) ad6676