AD7175-2 24-Bit, 250 kSPS, Sigma-Delta ADC with 20 µs Settling and True Rail-to-Rail Buffers

The AD7175-2 is a low noise, fast settling, multiplexed, 2-/4- channel (fully/pseudo differential) Σ-Δ analog-to-digital converter (ADC) for low bandwidth inputs. It has a maximum channel scan rate of 50 kSPS (20 µs) for fully settled data. The output data rates range from 5 SPS to 250 kSPS.

The AD7175-2 integrates key analog and digital signal conditioning blocks to allow users to configure an individual setup for each analog input channel in use. Each feature can be user selected on a per channel basis. Integrated true rail-to-rail buffers on the analog inputs and external reference inputs provide easy to drive high impedance inputs. The precision 2.5 V low drift (2 ppm/°C) band gap internal reference (with output reference buffer) adds embedded functionality to reduce external component count.

The digital filter allows simultaneous 50 Hz/60 Hz rejection at 27.27 SPS output data rate. The user can switch between different filter options according to the demands of each channel in the application. The ADC automatically switches through each selected channel. Further digital processing functions include offset and gain calibration registers, configurable on a per channel basis.

The device operates with a 5 V AVDD1, or ±2.5 V AVDD1/AVSS, and 2 V to 5 V AVDD2 and IOVDD supplies. The specified operating temperature range is −40°C to +105°C. The AD7175-2 is in a 24-lead TSSOP package.

Applications

Features and Benefits
  • Fast and flexible output rate: 5 SPS to 250 kSPS
  • Channel scan data rate of 50 kSPS/channel (20 µs settling)
  • Performance specifications
    • 17.2 noise free bits at 250 kSPS
    • 20 noise free bits at 2.5 kSPS
    • 24 noise free bits at 20 SPS
    • INL: ±1 ppm of FSR
  • 17.2 noise free bits at 250 kSPS
  • 20 noise free bits at 2.5 kSPS
  • 24 noise free bits at 20 SPS
  • INL: ±1 ppm of FSR
  • 85 dB rejection of 50 Hz and 60 Hz with 50 ms settling
  • User configurable input channels
    • 2 fully differential channels or 4 single-ended channels
    • Crosspoint multiplexer
  • 2 fully differential channels or 4 single-ended channels
  • Crosspoint multiplexer
  • On-chip 2.5 V reference (±2 ppm/°C drift)
  • True rail-to-rail analog and reference input buffers
  • Internal or external clock
  • Power supply: AVDD1 = 5 V, AVDD2 = IOVDD = 2 V to 5 V
    • Split supply with AVDD1/AVSS at ±2.5 V
  • Split supply with AVDD1/AVSS at ±2.5 V
  • ADC current: 8.4 mA
  • Temperature range: −40°C to +105°C
  • 3- or 4-wire serial digital interface (Schmitt trigger on SCLK)
    • Serial port interface (SPI), QSPI, MICROWIRE, and DSP compatible
  • Serial port interface (SPI), QSPI, MICROWIRE, and DSP compatible
  • Analog to Digital Converters
    IBIS Models
    Design Tools
    Software & Systems Requirements
    Data Sheets
    Documentnote
    AD7175-2: 24-Bit, 250 kSPS, Sigma-Delta ADC with 20 μs Settling and True Rail-to-Rail Buffers Data Sheet (Rev. B)PDF 1.24 M
    User Guides
    Documentnote
    UG-741: Evaluating the AD7175-2 24-Bit, 250 kSPS, Sigma-Delta ADC with 20 μs Settling and Integrated Analog Input BufferPDF 826.67 K
    Technical Books
    Documentnote
    Order Information
    Part NumberPackagePacking QtyTemp RangePrice 100-499Price 1000+RoHS
    AD7175-2BRUZ Production24 ld TSSOPOTH 62-40 to 105C12.6811.85Y
    AD7175-2BRUZ-RL Production24 ld TSSOPREEL 2500-40 to 105C011.85Y
    AD7175-2BRUZ-RL7 Production24 ld TSSOPREEL 1000-40 to 105C011.85Y
    Evaluation Boards
    Part NumberDescriptionPriceRoHS
    EVAL-AD7175-2SDZEvaluation Board89Y
    EVAL-SDP-CB1ZEvaluation Controller Board99Y
    Reference Materials
    AD7175-2:24位、250 kSPS Sigma 型ADC 具有20μMS建立时间和真轨到轨缓冲器 (Rev. B) ad7175-2
    AD7175-2: 24-Bit, 250 kSPS, Sigma-Delta ADC with 20 μs Settling and True Rail-to-Rail Buffers Data Sheet (Rev. B) ad7175-2
    AD7175-2 IBIS Model ad7175-2
    AD7175-2 Digital Filter Frequency Response Model ad7175-2
    AD717x Eval+ Software ad7176-2
    UG-741: Evaluating the AD7175-2 24-Bit, 250 kSPS, Sigma-Delta ADC with 20 μs Settling and Integrated Analog Input Buffer ad7175-2
    MT-023: ADC架构IV:Σ-Δ型ADC高级概念和应用 ad7176-2
    MT-022: ADC架构III:Σ-Δ型ADC基础 ad7176-2
    CN0363:带可编程增益跨阻放大器和数字同步检波功能的双通道色度计 adg704
    Σ-Δ型ADC拓扑结构基本原理:第一部分 ad7175-2
    Σ-Δ型ADC拓扑结构基本原理:第二部分 ad7175-2