AD7177-2 32-Bit, 10 kSPS, Sigma-Delta ADC with 100 µs Settling and True Rail-to-Rail Buffers

The AD7177-2 is a 32-bit low noise, fast settling, multiplexed, 2-/4-channel (fully/pseudo differential) Σ-Δ analog-to-digital converter (ADC) for low bandwidth inputs. It has a maximum channel scan rate of 10 kSPS (100 µs) for fully settled data. The output data rates range from 5 SPS to 10 kSPS.

The AD7177-2 integrates key analog and digital signal conditioning blocks to allow users to configure an individual setup for each analog input channel in use. Each feature can be user selected on a per channel basis. Integrated true rail-to-rail buffers on the analog inputs and external reference inputs provide easy to drive high impedance inputs. The precision 2.5 V low drift (2 ppm/°C) band gap internal reference (with output reference buffer) adds embedded functionality to reduce external component count.

The digital filter allows simultaneous 50 Hz and 60 Hz rejection at a 27.27 SPS output data rate. The user can switch between different filter options according to the demands of each channel in the application. The ADC automatically switches through each selected channel. Further digital processing functions include offset and gain calibration registers, configurable on a per channel basis.

The device operates with a 5 V AVDD1 supply, or with ±2.5 V AVDD1/AVSS, and 2 V to 5 V AVDD2 and IOVDD supplies. The specified operating temperature range is −40°C to +105°C. The AD7177-2 is available in a 24-lead TSSOP package.

Applications

Features and Benefits
  • 32-bit data output
  • Fast and flexible output rate: 5 SPS to 10 kSPS
  • Channel scan data rate of 10 kSPS/channel (100 µs settling)
  • Performance specifications
  • 19.1 noise free bits at 10 kSPS
  • 20.2 noise free bits at 2.5 kSPS
  • 24.6 noise free bits at 5 SPS
  • INL: ±1 ppm of FSR
  • 85 dB filter rejection of 50 Hz and 60 Hz with 50 ms settling
  • User configurable input channels
  • 2 fully differential channels or 4 single-ended channels
  • Crosspoint multiplexer
  • On-chip 2.5 V reference (±2 ppm/°C drift)
  • True rail-to-rail analog and reference input buffers
  • Internal or external clock
  • See data sheet for additional features
  • Analog to Digital Converters
    IBIS Models
    Design Tools
    Reference Designs
    Software & Systems Requirements
    Data Sheets
    Documentnote
    AD7177-2: 32-Bit, 10 kSPS, Sigma-Delta ADC with 100 μs Settling and True Rail-to-Rail Buffers Data Sheet (Rev. B)PDF 925.75 K
    User Guides
    Documentnote
    UG-849: Evaluating the AD7177-2 32-Bit, 10 kSPS, Sigma-Delta ADC with 100 µs Settling and Integrated Analog Input BuffersPDF 924.21 K
    Technical Books
    Documentnote
    Order Information
    Part NumberPackagePacking QtyTemp RangePrice 100-499Price 1000+RoHS
    AD7177-2BRUZ Production24 ld TSSOPOTH 62-40 to 105C15.6814.65Y
    AD7177-2BRUZ-RL7 Production24 ld TSSOPREEL 1000-40 to 105C014.65Y
    Evaluation Boards
    Part NumberDescriptionPriceRoHS
    EVAL-AD7177-2SDZEvaluation Board59Y
    EVAL-SDP-CB1ZSDP Controller Board99Y
    Reference Materials
    AD7177-2:32 位、 10 kSPS Σ-Δ 型 ADC , 100 μs 建立时间,集成真轨到轨缓冲器 (Rev. B) ad7177-2
    AD7177-2: 32-Bit, 10 kSPS, Sigma-Delta ADC with 100 μs Settling and True Rail-to-Rail Buffers Data Sheet (Rev. B) ad7177-2
    AD7177-2 IBIS Model ad7177-2
    AD7177-2 Digital Filter Frequency Response Model ad7177-2
    CN0292 Design & Integration Files adg1204
    CN0364 设计与集成文件 adg704
    AD717x Eval+ Software ad7176-2
    UG-849: Evaluating the AD7177-2 32-Bit, 10 kSPS, Sigma-Delta ADC with 100 µs Settling and Integrated Analog Input Buffers ad7177-2
    MT-023: ADC架构IV:Σ-Δ型ADC高级概念和应用 ad7176-2
    MT-022: ADC架构III:Σ-Δ型ADC基础 ad7176-2
    CN0292:用于工业电平信号的完全隔离、鲁棒、4通道、多路复用数据采集系统 adg1204
    CN0364:兼容 HART 的 PLC/DCS 四通道电压、电流输入 adg704
    Σ-Δ型ADC拓扑结构基本原理:第一部分 ad7175-2
    Σ-Δ型ADC拓扑结构基本原理:第二部分 ad7175-2