AD9142A Dual, 16-Bit, 1600 MSPS, TxDAC+ Digital-to-Analog Converter

Wide signal bandwidth (BW) enables emerging wideband and multiband wireless applications. Advanced low spurious and distortion design techniques provide high quality synthesis of wideband signals from baseband to high intermediate frequencies. Very small inherent latency variation simplifies both software and hardware design in the system. It allows easy multichip synchronization for most applications. New low power architecture improves power efficiency (mW/MHz/channel) by 30%. Input signal power and FIFO error detection simplify designs for downstream analog circuitry protection. Programmable transmit enable function allows easy design balance between power consumption and wakeup time. APPLICATIONS

The AD9142A is a dual, 16-bit, high dynamic range digital-to-analog converter (DAC) that provides a sample rate of 1600 MSPS, permitting a multicarrier generation up to the Nyquist frequency. The AD9142A TxDAC+® includes features optimized for direct conversion transmit applications, including complex digital modulation, input signal power detection, and gain, phase, and offset compensation. The DAC outputs are optimized to interface seamlessly with analog quadrature modulators, such as the ADL537x F-MOD series and the ADRF670x series from Analog Devices, Inc. A 3-wire serial port interface provides for the programming/readback of many internal parameters. Full-scale output current can be programmed over a range of 9 mA to 33 mA. The AD9142A is available in a 72-lead LFCSP.

PRODUCT HIGHLIGHTS

Wide signal bandwidth (BW) enables emerging wideband and multiband wireless applications.
Advanced low spurious and distortion design techniques provide high quality synthesis of wideband signals from baseband to high intermediate frequencies.
Very small inherent latency variation simplifies both software and hardware design in the system. It allows easy multichip synchronization for most applications.
New low power architecture improves power efficiency (mW/MHz/channel) by 30%.
Input signal power and FIFO error detection simplify designs for downstream analog circuitry protection.
Programmable transmit enable function allows easy design balance between power consumption and wakeup time.

Features and Benefits

Supports input data rate up to 575 MHz
Very small inherent latency variation: <2 DAC clock cycles
Proprietary low spurious and distortion design
6-carrier GSM ACLR = 79 dBc at 200 MHz IF
SFDR > 85 dBc (bandwidth = 300 MHz) at ZIF
Flexible 16-bit LVDS interface
Supports word and byte load
Data interface DLL
Sample error detection and parity

Multiple chip synchronization
Fixed latency and data generator latency compensation
Selectable 2×, 4×, 8× interpolation filter
Low power architecture
fS/4 power saving coarse mixer
Input signal power detection
Emergency stop for downstream analog circuitry protection
FIFO error detection
See datasheet for additional features