AD9444 14-Bit, 80 MSPS A/D Converter _ BDTIC a Leading Distributor in China

AD9444 14-Bit, 80 MSPS A/D Converter

The AD9444 is a 14-bit monolithic, sampling analog-to-digital converter (ADC) with an on-chip, track-and-hold circuit and is optimized for power, small size, and ease of use. The product operates at up to an 80 MSPS conversion rate and is optimized for multicarrier, multimode receivers, such as those found in cellular infrastructure equipment. High performance: Outstanding SFDR performance for mul-ticarrier, multimode 3G and 4G cellular base station receivers. Ease of use: On-chip reference and track-and-hold. An output clock simplifies data capture. Packaged in a Pb-free, 100-lead TQFP/EP. Clock DCS maintains overall ADC performance over a wide range of clock pulse widths. OR (out-of-range) outputs indicate when the signal is beyond the selected input range.

The ADC requires 3.3 V and 5.0 V power supplies and a low voltage differential input clock for full performance operation. No external reference or driver components are required for many applications. Data outputs are LVDS-compatible (ANSI-644) or CMOS-compatible and include the means to reduce the overall current needed for short trace distances.

Optional features allow users to implement various selectable operating conditions, including data format select and output data mode.

The AD9444 is available in a 100-lead surface-mount plastic package (100-lead TQFP/EP) specified over the industrial temperature range (−40°C to +85°C).

Product Highlights

High performance: Outstanding SFDR performance for mul-ticarrier, multimode 3G and 4G cellular base station receivers.
Ease of use: On-chip reference and track-and-hold. An output clock simplifies data capture.
Packaged in a Pb-free, 100-lead TQFP/EP.
Clock DCS maintains overall ADC performance over a wide range of clock pulse widths.
OR (out-of-range) outputs indicate when the signal is beyond the selected input range.

Applications

Multicarrier, multimode cellular receivers
Antenna array positioning
Power amplifier linearization
Broadband wireless Radar, infared imaging
Communications instrumentation

Features and Benefits

80 MSPS guaranteed sampling rate
100 dB two-tone SFDR with 69.3 MHz and 70.3 MHz
73.1 dB SNR with 70 MHz input
97 dBc SFDR with 70 MHz input
Excellent linearity
DNL = ±0.4 LSB typical
INL = ±0.6 LSB typical

1.2 W power dissipation
3.3 V and 5 V supply operation
2.0 V p-p differential full-scale input
LVDS outputs (ANSI-644 compatible)
Data format select
Output clock available

Analog to Digital Converters

AD9444 IBIS Models

AD9444BSVZ .IBS

Data Sheets

Document	note
AD9444: 14-Bit, 80 MSPS, A/D Converter Data Sheet (Rev. 0)	PDF 1291 kB

Application Notes

Document	note
AN-905: Visual Analog Converter Evaluation Tool Version 1.0 User Manual (Rev. 0)	PDF 2124 kB
AN-835: Understanding High Speed ADC Testing and Evaluation (Rev. B)	PDF 985 kB
AN-501: Aperture Uncertainty and ADC System Performance (Rev. A)	PDF 227 kB
AN-282: Fundamentals of Sampled Data Systems	PDF 2131 kB
AN-756: Sampled Systems and the Effects of Clock Phase Noise and Jitter (Rev. 0)	PDF 291.7 K
AN-935: Designing an ADC Transformer-Coupled Front End (Rev. 0)	PDF 363 kB
AN-345: Grounding for Low-and-High-Frequency Circuits	PDF 455 kB
AN-586: LVDS Outputs for High Speed A/D Converters (Rev. 0)	PDF 207 kB
AN-1142: Techniques for High Speed ADC PCB Layout (Rev. 0)	PDF 392 kB
AN-737: How ADIsimADC Models an ADC (Rev. B)	PDF 373 kB
AN-807: Multicarrier WCDMA Feasibility (Rev. 0)	PDF 969 kB
AN-808: Multicarrier CDMA2000 Feasibility (Rev. 0)	PDF 1535 kB
AN-715: A First Approach to IBIS Models: What They Are and How They Are Generated (Rev. 0)	PDF 370.2 K
AN-741: Little Known Characteristics of Phase Noise (Rev. 0)	PDF 1679 kB