AD9513 800 MHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs

The AD9513 features a three-output clock distribution IC in a design that emphasizes low jitter and phase noise to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this part.

There are three independent clock outputs that can be set to either LVDS or CMOS levels. These outputs operate to 800 MHz in LVDS mode and to 250 MHz in CMOS mode.

Each output has a programmable divider that can be set to divide by a selected set of integers ranging from 1 to 32. The phase of one clock output relative to the other clock output can be set by means of a divider phase select function that serves as a coarse timing adjustment.

One of the outputs features a delay element with three selectable full-scale delay values (1.5 ns, 5 ns, and 10 ns), each with 16 steps of fine adjustment.

The AD9513 does not require an external controller for operation or setup. The device is programmed by means of 11 pins (S0 to S10) using 4-level logic. The programming pins are internally biased to ⅓ VS. The VREF pin provides a level of ⅔ VS. VS (3.3 V) and GND (0 V) provide the other two logic levels.

The AD9513 is ideally suited for data converter clocking applications where maximum converter performance is achieved by encode signals with subpicosecond jitter.

The AD9513 is available in a 32-lead LFCSP and operates from a single 3.3 V supply. The temperature range is −40°C to +85°C.

Applications
  • Low jitter, low phase noise clock distribution
  • Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
  • High performance wireless transceivers
  • High performance instrumentation
  • Broadband infrastructure
  • ATE
Features and Benefits
  • 1.6 GHz differential clock input
  • 3 programmable dividers, in range from 1 to 32
    Phase select for output-to-output coarse delay adjust
  • 3 800 MHz/250 MHz LVDS/CMOS clock outputs
    Additive output jitter 300 fs rms/290 fs rms
    Time delays up to 10 ns
  • Device configured with 4-level logic pins
  • Space-saving, 32-lead LFCSP
Clock & Timing
RF & Microwave
AD9513 IBIS Models
Data Sheets
Documentnote
AD9513: 800 MHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs Data Sheet (Rev. 0)PDF 603 kB
Application Notes
Documentnote
AN-0974: Multicarrier TD-SCMA FeasibilityPDF 634 kB
AN-501: Aperture Uncertainty and ADC System Performance (Rev. A)PDF 227 kB
AN-756: Sampled Systems and the Effects of Clock Phase Noise and Jitter (Rev. 0)PDF 291.7 K
AN-769: Generating Multiple Clock Outputs from the AD9540 (Rev. 0)PDF 0
AN-939: Super-Nyquist Operation of the AD9912 Yields a High RF Output Signal (Rev. 0)PDF 221 kB
AN-837: DDS-Based Clock Jitter Performance vs. DAC Reconstruction Filter Performance (Rev. 0)PDF 313 kB
AN-823: Direct Digital Synthesizers in Clocking Applications Time (Rev. 0)PDF 115 kB
AN-927: Determining if a Spur is Related to the DDS/DAC or to Some Other Source (For Example, Switching Supplies) (Rev. 0)PDF 170 kB
AN-873: Lock Detect on the ADF4xxx Family of PLL Synthesizers (Rev. 0)PDF 207 kB
AN-741: Little Known Characteristics of Phase Noise (Rev. 0)PDF 1679 kB
Frequently Asked Questions
Documentnote
Order Information
Part NumberPackagePacking QtyTemp RangePrice 100-499Price 1000+RoHS
AD9513BCPZ Production32 ld LFCSP (5x5mm)OTH 490-40 to 85C6.415.45Y
AD9513BCPZ-REEL7 Production32 ld LFCSP (5x5mm)REEL 1500-40 to 85C05.45Y
Evaluation Boards
Part NumberDescriptionPriceRoHS
AD9513/PCBZEvaluation Board190Y
Reference Materials
AD9513: 800 MHz Clock Distribution IC, Dividers, Delay Adjust, Three Outputs Data Sheet (Rev. 0) ad9513
AD9513 (All Models/All Speed Grades) ad9513
AN-0974: Multicarrier TD-SCMA Feasibility ad6655
AN-501: Aperture Uncertainty and ADC System Performance (Rev. A) ad9220
AN-756: Sampled Systems and the Effects of Clock Phase Noise and Jitter (Rev. 0) ad9220
AN-769: Generating Multiple Clock Outputs from the AD9540 (Rev. 0) ad9540
AN-939: Super-Nyquist Operation of the AD9912 Yields a High RF Output Signal (Rev. 0) ad9540
AN-837: DDS-Based Clock Jitter Performance vs. DAC Reconstruction Filter Performance (Rev. 0) ad9856
AN-823: Direct Digital Synthesizers in Clocking Applications Time (Rev. 0) ad9856
AN-927: Determining if a Spur is Related to the DDS/DAC or to Some Other Source (For Example, Switching Supplies) (Rev. 0) ad9540
AN-769: 基于AD9540产生多时钟输出 (Rev. 0) ad9540
AN-0974: TD-SCMA多载波系统可行性研究 (Rev. 0) ad8376
AN-873: ADF4xxx系列PLL频率合成器的锁定检测 (Rev. 0) ad9540
AN-939: 利用AD9912的超奈奎斯特频率操作得到高RF输出信号 (Rev. 0) ad9540
AN-927: 确定杂散来源是DDS/DAC还是其他器件(例如开关电源)[中文版] (Rev. 0) ad9540
AN-837: 基于DDS的时钟抖动性能与DAC重构滤波器性能的关系[中文版] (Rev. 0) ad9540
AN-873: Lock Detect on the ADF4xxx Family of PLL Synthesizers (Rev. 0) ad9540
AN-823: 时钟应用中的直接数字频率合成器[中文版] (Rev. 0) ad9540
AN-756: 系统采样以及时钟相位噪声和抖动的影响[中文版] (Rev. 0) ad9540
AN-501: 孔径不确定度与ADC系统性能[中文版] (Rev. A) ad9540
AN-741: Little Known Characteristics of Phase Noise (Rev. 0) ad9221
AN-741: 鲜为人知的相位噪声特性 ad9540
RF Source Booklet adf9010
CN-0109: Low Jitter Sampling Clock Generator for High Performance ADCs Using... ad9512