AD9516-2 14-Output Clock Generator with Integrated 2.2 GHz VCO

The AD9516-21 provides a multi-output clock distribution function with subpicosecond jitter performance, along with an on-chip PLL and VCO. The on-chip VCO tunes from 2.05 GHz to 2.33 GHz. Optionally, an external VCO/VCXO of up to 2.4 GHz can be used.

The AD9516-2 emphasizes low jitter and phase noise to maximize data converter performance, and it can benefit other applications with demanding phase noise and jitter requirements.

The AD9516-2 features six LVPECL outputs (in three pairs) and four LVDS outputs (in two pairs). Each LVDS output can be reconfigured as two CMOS outputs. The LVPECL outputs operate to 1.6 GHz, the LVDS outputs operate to 800 MHz, and the CMOS outputs operate to 250 MHz.

Each pair of outputs has dividers that allow both the divide ratio and coarse delay (or phase) to be set. The range of division for the LVPECL outputs is 1 to 32. The LVDS/CMOS outputs allow a range of divisions up to a maximum of 1024.

The AD9516-0 is available in a 64-lead LFCSP and can be operated from a single 3.3 V supply. An external VCO, which requires an extended voltage range, can be accommodated by connecting the charge pump supply (VCP) to 5 V. A separate LVPECL power supply can be from 2.5 V to 3.3 V (nominal).

The AD9516-2 is specified for operation over the standard industrial range of −40°C to +85°C.

Applications
  • Low jitter, low phase noise clock distribution
  • 10/40/100 Gb/sec networking line cards, including SONET, Synchronous Ethernet, OTU2/3/4
  • Forward error correction (G.710)
  • Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
  • High performance wireless transceivers
  • ATE and high performance instrumentation

1AD9516 is used throughout to refer to all the members of the AD9516 family. However, when AD9516-2 is used, it is referring to that specific member of the AD9516 family.

Features and Benefits
  • Low phase noise, phase-locked loop (PLL) -- On-chip VCO tunes from 2.05 GHz to 2.33 GHz -- External VCO/VCXO to 2.4 GHz optional -- 1 differential or 2 single-ended reference inputs
    • 6 pairs of 1.6 GHz LVPECL outputs -- Each output pair shares a 1-to-32 divider with coarse phase delay -- Additive output jitter: 225 fs rms -- Channel-to-channel skew paired outputs of <10 ps
  • 4 pairs of 800 MHz LVDS clock outputs -- Each output pair shares two cascaded 1-to-32 dividers with coarse phase delay -- Additive output jitter: 275 fs rms
    • Automatic synchronization of all outputs on power-up
    • Manual output synchronization available
    • 64-lead LFCSP
    • See datasheet for additional features
Clock & Timing
RF & Microwave
AD9516 IBIS Models
Reference Designs
Data Sheets
Documentnote
AD9516-2: 14-Output Clock Generator with Integrated 2.2 GHz VCO Data Sheet (Rev. C)PDF 940 kB
Application Notes
Documentnote
AN-0974: Multicarrier TD-SCMA FeasibilityPDF 634 kB
AN-835: Understanding High Speed ADC Testing and Evaluation (Rev. B)PDF 985 kB
AN-501: Aperture Uncertainty and ADC System Performance (Rev. A)PDF 227 kB
AN-0983: Introduction to Zero-Delay Clock Timing TechniquesPDF 162 kB
AN-756: Sampled Systems and the Effects of Clock Phase Noise and Jitter (Rev. 0)PDF 291.7 K
AN-769: Generating Multiple Clock Outputs from the AD9540 (Rev. 0)PDF 0
AN-939: Super-Nyquist Operation of the AD9912 Yields a High RF Output Signal (Rev. 0)PDF 221 kB
AN-837: DDS-Based Clock Jitter Performance vs. DAC Reconstruction Filter Performance (Rev. 0)PDF 313 kB
AN-823: Direct Digital Synthesizers in Clocking Applications Time (Rev. 0)PDF 115 kB
AN-927: Determining if a Spur is Related to the DDS/DAC or to Some Other Source (For Example, Switching Supplies) (Rev. 0)PDF 170 kB
AN-873: Lock Detect on the ADF4xxx Family of PLL Synthesizers (Rev. 0)PDF 207 kB
AN-741: Little Known Characteristics of Phase Noise (Rev. 0)PDF 1679 kB
User Guides
Documentnote
UG-093: Evaluation Board User Guide for the Dual, Continuous Time Sigma-Delta ModulatorPDF 1449 kB
UG-075: AD9516-x, AD9517-x, and AD9518-x Evaluation Board User GuidePDF 1089 kB
Frequently Asked Questions
Documentnote
Order Information
Part NumberPackagePacking QtyTemp RangePrice 100-499Price 1000+RoHS
AD9516-2BCPZ Production64 ld LFCSP (9x9mm, 6.20mm exposed pad)OTH 260-40 to 85C8.357.1Y
AD9516-2BCPZ-REEL7 Production64 ld LFCSP (9x9mm, 6.20mm exposed pad)REEL 750-40 to 85C07.1Y
Evaluation Boards
Part NumberDescriptionPriceRoHS
AD9516-2/PCBZEvaluation Board190Y
Reference Materials
AD9516-2: 14-Output Clock Generator with Integrated 2.2 GHz VCO Data Sheet (Rev. C) ad9516-2
AD9516 (All Models/All Speed Grades) ad9516-0
CN0243 Design & Integration Files ad9516-0
AD9516参考代码 ad9516-0
AN-0974: Multicarrier TD-SCMA Feasibility ad6655
AN-835: Understanding High Speed ADC Testing and Evaluation (Rev. B) ad9220
AN-501: Aperture Uncertainty and ADC System Performance (Rev. A) ad9220
AN-0983: Introduction to Zero-Delay Clock Timing Techniques ad9510
AN-756: Sampled Systems and the Effects of Clock Phase Noise and Jitter (Rev. 0) ad9220
AN-769: Generating Multiple Clock Outputs from the AD9540 (Rev. 0) ad9540
AN-939: Super-Nyquist Operation of the AD9912 Yields a High RF Output Signal (Rev. 0) ad9540
AN-837: DDS-Based Clock Jitter Performance vs. DAC Reconstruction Filter Performance (Rev. 0) ad9856
AN-823: Direct Digital Synthesizers in Clocking Applications Time (Rev. 0) ad9856
AN-927: Determining if a Spur is Related to the DDS/DAC or to Some Other Source (For Example, Switching Supplies) (Rev. 0) ad9540
AN-835: 高速ADC测试和评估 (Rev. 0) ad9510
AN-769: 基于AD9540产生多时钟输出 (Rev. 0) ad9540
AN-0974: TD-SCMA多载波系统可行性研究 (Rev. 0) ad8376
AN-873: ADF4xxx系列PLL频率合成器的锁定检测 (Rev. 0) ad9540
AN-0983: 零延迟时钟定时技术简介 (Rev. 0) ad9510
AN-939: 利用AD9912的超奈奎斯特频率操作得到高RF输出信号 (Rev. 0) ad9540
AN-927: 确定杂散来源是DDS/DAC还是其他器件(例如开关电源)[中文版] (Rev. 0) ad9540
AN-837: 基于DDS的时钟抖动性能与DAC重构滤波器性能的关系[中文版] (Rev. 0) ad9540
AN-873: Lock Detect on the ADF4xxx Family of PLL Synthesizers (Rev. 0) ad9540
AN-823: 时钟应用中的直接数字频率合成器[中文版] (Rev. 0) ad9540
AN-756: 系统采样以及时钟相位噪声和抖动的影响[中文版] (Rev. 0) ad9540
AN-501: 孔径不确定度与ADC系统性能[中文版] (Rev. A) ad9540
AN-741: Little Known Characteristics of Phase Noise (Rev. 0) ad9221
AN-741: 鲜为人知的相位噪声特性 ad9540
UG-093: Evaluation Board User Guide for the Dual, Continuous Time Sigma-Delta Modulator ad9516-0
UG-075: AD9516-x, AD9517-x, and AD9518-x Evaluation Board User Guide ad9516-0
RF Source Booklet adf9010
CN0243: 采用外部单频率参考的高动态范围RF发射器信号链,适合DAC采样时钟和IQ调节器本振生成 ad9516-0