AD9516-3 14-Output Clock Generator with Integrated 2.0 GHz VCO

The AD9516-31 provides a multi-output clock distribution function with subpicosecond jitter performance, along with an on-chip PLL and VCO. The on-chip VCO tunes from 1.75 GHz to 2.25 GHz. Optionally, an external VCO/VCXO of up to 2.4 GHz can be used. Applications

The AD9516-3 emphasizes low jitter and phase noise to maximize data converter performance, and it can benefit other applications with demanding phase noise and jitter requirements.

The AD9516-3 features six LVPECL outputs (in three pairs) and four LVDS outputs (in two pairs). Each LVDS output can be reconfigured as two CMOS outputs. The LVPECL outputs operate to 1.6 GHz, the LVDS outputs operate to 800 MHz, and the CMOS outputs operate to 250 MHz.

Each pair of outputs has dividers that allow both the divide ratio and coarse delay (or phase) to be set. The range of division for the LVPECL outputs is 1 to 32. The LVDS/CMOS outputs allow a range of divisions up to a maximum of 1024.

The AD9516-3 is available in a 64-lead LFCSP and can be operated from a single 3.3 V supply. An external VCO, which requires an extended voltage range, can be accommodated by connecting the charge pump supply (VCP) to 5 V. A separate LVPECL power supply can be from 2.5 V to 3.3 V (nominal).

The AD9516-3 is specified for operation over the standard industrial range of −40°C to +85°C.

1 AD9516 is used throughout to refer to all the members of the AD9516 family. However, when AD9516-3 is used it is referring to that specific member of the AD9516 family.

Features and Benefits

Low phase noise, phase-locked loop (PLL)
-- On-chip VCO tunes from 1.75 GHz to 2.25 GHz
-- External VCO/VCXO to 2.4 GHz optional
-- 1 differential or 2 single-ended reference inputs
6 pairs of 1.6 GHz LVPECL outputs
-- Each output pair shares a 1-to-32 divider with coarse phase delay
-- Additive output jitter:
225 fs rms
-- Channel-to-channel skew paired outputs of <10 ps

4 pairs of 800 MHz LVDS clock outputs
-- Each output pair shares two cascaded 1-to-32 dividers with coarse phase delay
--Additive output jitter:
275 fs rms
Automatic synchronization of all outputs on power-up
Manual output synchronization available
64-lead LFCSP
See datasheet for additional features

Data Sheets

Document	note
AD9516-3: 14-Output Clock Generator with Integrated 2.0 GHz VCO Data Sheet (Rev. C)	PDF 952 kB

Application Notes

Document	note
AN-0974: Multicarrier TD-SCMA Feasibility	PDF 634 kB
AN-835: Understanding High Speed ADC Testing and Evaluation (Rev. B)	PDF 985 kB
AN-501: Aperture Uncertainty and ADC System Performance (Rev. A)	PDF 227 kB
AN-0983: Introduction to Zero-Delay Clock Timing Techniques	PDF 162 kB
AN-756: Sampled Systems and the Effects of Clock Phase Noise and Jitter (Rev. 0)	PDF 291.7 K
AN-769: Generating Multiple Clock Outputs from the AD9540 (Rev. 0)	PDF 0
AN-939: Super-Nyquist Operation of the AD9912 Yields a High RF Output Signal (Rev. 0)	PDF 221 kB
AN-837: DDS-Based Clock Jitter Performance vs. DAC Reconstruction Filter Performance (Rev. 0)	PDF 313 kB
AN-823: Direct Digital Synthesizers in Clocking Applications Time (Rev. 0)	PDF 115 kB
AN-927: Determining if a Spur is Related to the DDS/DAC or to Some Other Source (For Example, Switching Supplies) (Rev. 0)	PDF 170 kB
AN-873: Lock Detect on the ADF4xxx Family of PLL Synthesizers (Rev. 0)	PDF 207 kB
AN-741: Little Known Characteristics of Phase Noise (Rev. 0)	PDF 1679 kB

User Guides

Document	note
UG-093: Evaluation Board User Guide for the Dual, Continuous Time Sigma-Delta Modulator	PDF 1449 kB
UG-075: AD9516-x, AD9517-x, and AD9518-x Evaluation Board User Guide	PDF 1089 kB

Frequently Asked Questions

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Order Information

Part Number	Package	Packing Qty	Temp Range	Price 100-499	Price 1000+	RoHS
AD9516-3BCPZ Production	64 ld LFCSP (9x9mm, 6.20mm exposed pad)	OTH 260	-40 to 85C	8.35	7.1	Y
AD9516-3BCPZ-REEL7 Production	64 ld LFCSP (9x9mm, 6.20mm exposed pad)	REEL 750	-40 to 85C	0	7.1	Y