AD9554 Quad PLL, Quad Input, 8-output Multiservice Line Card Adaptive Clock Translator

The AD9554 is a low loop bandwidth clock translator that provides jitter cleanup and synchronization for many systems, including synchronous optical networks (SONET/SDH). The AD9554 generates an output clock synchronized to up to four external input references. The digital PLL (DPLL) allows for reduction of input time jitter or phase noise associated with the external references. The digitally controlled loop and holdover circuitry of the AD9554 continuously generates a low jitter output clock even when all reference inputs have failed.

The AD9554 operates over an industrial temperature range of −40°C to +85°C. If a single or dual DPLL version of this devices is needed, refer to the AD9557 or AD9559, respectively.

Applications
  • Network synchronization, including synchronous Ethernet and synchronous digital hierarchy (SDH) to optical transport network (OTN) mapping/demapping
  • Cleanup of reference clock jitter
  • SONET/SDH clocks up to OC-192, including FEC
  • Stratum 3 holdover, jitter cleanup, and phase transient control
  • Cable infrastructure
  • Data communications
Features and Benefits
  • Supports GR-1244 Stratum 3 stability in holdover mode
  • Supports smooth reference switchover with virtually no disturbance on output phase
  • Supports Telcordia GR-253 jitter generation, transfer, and tolerance for SONET/SDH up to OC-192 systems
  • Supports ITU-T G.8262 synchronous Ethernet slave clocks
  • Supports ITU-T G.823, ITU-T G.824, ITU-T G.825, and ITU-T G.8261
  • Auto/manual holdover and reference switchover
  • Adaptive clocking allows dynamic adjustment of feedback dividers for use in OTN mapping/demapping applications
  • Quad digital phase-locked loop (DPLL) architecture with four reference inputs (single-ended or differential)
  • 4x4 crosspoint allows any reference input to drive any PLL
  • See datasheet for additional features
Clock & Timing
RF & Microwave
Data Sheets
Documentnote
AD9554: Quad PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator Data Sheet (Rev. B)PDF 1.21 M
Order Information
Part NumberPackagePacking QtyTemp RangePrice 100-499Price 1000+RoHS
AD9554BCPZ Production72 ld LFCSP (10x10mm, 7.1mm exposed pad) OTH 168-40 to 85C25.0921.33Y
AD9554BCPZ-REEL Production72 ld LFCSP (10x10mm, 7.1mm exposed pad) REEL 2000-40 to 85C021.33Y
AD9554BCPZ-REEL7 Production72 ld LFCSP (10x10mm, 7.1mm exposed pad) REEL 400-40 to 85C25.0921.33Y
Evaluation Boards
Part NumberDescriptionPriceRoHS
AD9554/PCBZEvaluation Board190Y
AD9554: Quad PLL, Quad Input, Multiservice Line Card Adaptive Clock Translator Data Sheet (Rev. B) ad9554