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AD9554-1 Quad PLL, Quad Input, 4-output Multiservice Line Card Adaptive Clock Translator

The AD9554-1 is a low loop bandwidth clock multiplier that provides jitter cleanup and synchronization for many systems, including synchronous optical networks (SONET/SDH). The AD9554-1 generates an output clock synchronized to up to four external input references. The digital PLL allows for reduction of input time jitter or phase noise associated with the external references. The digitally controlled loop and holdover circuitry of the AD9554-1continuously generates a low jitter output clock even when all reference inputs have failed. The AD9554-1 operates over an industrial temperature range of −40°C to +85°C. If a single DPLL version of this part is needed, refer to the AD9557 or AD9559, respectively.    APPLICATIONS Network synchronization, including synchronous Ethernet and SDH to OTN mapping/demapping  Cleanup of reference clock jitter  SONET/SDH clocks up to OC-192, including FEC  Stratum 3 holdover, jitter cleanup, and phase transient control  Wireless base station controllers  Cable infrastructure  Data communications  Professional Video

APPLICATIONS

• Network synchronization, including synchronous Ethernet and SDH to OTN mapping/demapping
• Cleanup of reference clock jitter
• SONET/SDH clocks up to OC-192, including FEC
• Stratum 3 holdover, jitter cleanup, and phase transient control
• Wireless base station controllers
• Cable infrastructure
• Data communications
• Professional Video

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