AD9680 14-Bit, 1.25 GSPS/1 GSPS/820 MSPS/500 MSPS JESD204B, Dual Analog-to-Digital Converter

Product Highlights Wide full power bandwidth supports IF sampling of signals up to 2 GHz. Buffered inputs with programmable input termination eases filter design and implementation. Four integrated wideband decimation filters and numerically controlled oscillator (NCO) blocks supporting multiband receivers. Flexible serial port interface (SPI) controls various product features and functions to meet specific system requirements. Programmable fast overrange detection. 9 mm × 9 mm, 64-lead LFCSP. Applications

The AD9680 is a dual, 14-bit, 1.25 GSPS/1 GSPS/820 MSPS/ 500 MSPS analog-to-digital converter (ADC). The device has an on-chip buffer and sample-and-hold circuit designed for low power, small size, and ease of use. This device is designed for sampling wide bandwidth analog signals of up to 2 GHz. The AD9680 is optimized for wide input bandwidth, high sampling rate, excellent linearity, and low power in a small package.

The dual ADC cores feature a multistage, differential pipelined architecture with integrated output error correction logic. Each ADC features wide bandwidth inputs supporting a variety of user-selectable input ranges. An integrated voltage reference eases design considerations.

The analog input and clock signals are differential inputs. Each ADC data output is internally connected to two digital downconverters (DDCs). Each DDC consists of up to five cascaded signal processing stages: a 12-bit frequency translator (NCO), and four half-band decimation filters. The DDCs are bypassed by default.

In addition to the DDC blocks, the AD9680 has several functions that simplify the automatic gain control (AGC) function in the communications receiver. The programmable threshold detector allows monitoring of the incoming signal power using the fast detect output bits of the ADC. If the input signal level exceeds the programmable threshold, the fast detect indicator goes high. Because this threshold indicator has low latency, the user can quickly turn down the system gain to avoid an overrange condition at the ADC input.

Users can configure the Subclass 1 JESD204B-based high speed serialized output in a variety of one-, two-, or four-lane configurations, depending on the DDC configuration and the acceptable lane rate of the receiving logic device. Multiple device synchronization is supported through the SYSREF± and SYNCINB± input pins.

The AD9680 has flexible power-down options that allow significant power savings when desired. All of these features can be programmed using a 1.8 V to 3.3 V capable, 3-wire SPI.

The AD9680 is available in a Pb-free, 64-lead LFCSP and is specified over the −40°C to +85°C industrial temperature range. This product is protected by a U.S. patent.

Features and Benefits

Pin compatible family supporting sample rates up to 1.25 GSPS
JESD204B (Subclass 1) coded serial digital outputs
1.65 W total power per channel at 1 GSPS (default settings)
SFDR = 85 dBFS at 340 MHz, 80 dBFS at 1 GHz
SNR = 65.3 dBFS at 340 MHz (AIN = −1.0 dBFS), 60.5 dBFS at 1 GHz (AIN = -1.0 dBFS)
ENOB = 10.8 bits at 10 MHz
DNL = ±0.5 LSB
INL = ±2.5 LSB
Noise density = −154 dBFS/Hz at 1 GSPS
1.25 V, 2.5 V, and 3.3 V dc supply operation
No missing codes
Internal ADC voltage reference
Flexible input range

Programmable termination impedance
2 GHz usable analog input full power bandwidth
95 dB channel isolation/crosstalk
Amplitude detect bits for efficient AGC implementation
2 integrated wideband digital processors per channel
Differential clock input
Integer clock divide by 1, 2, 4, or 8
Flexible JESD204B lane configurations
Small signal dither

Analog to Digital Converters

High Speed ADC > 10MSPS

Aerospace and Defense

Solutions

Data Sheets

Document	note
AD9680: 14-Bit, 1 GSPS/820 MSPS/500 MSPS JESD204B, Dual Analog-to-Digital Converter Data Sheet (Rev. C)	PDF 1754 kB

Application Notes

Document	note
AN-835: Understanding High Speed ADC Testing and Evaluation (Rev. B)	PDF 985 kB

Order Information

Part Number	Package	Packing Qty	Temp Range	Price 100-499	Price 1000+	RoHS
AD9680BCPZ-1000 Production	64 ld LFCSP (9x9mm, 7.6mm exposed pad)	OTH 260	-40 to 85C	687.5	584.38	Y
AD9680BCPZ-1250 Production	LFCSP:LEADFRM CHIP SCALE	OTH 260	-40 to 85C	815	692.75	Y
AD9680BCPZ-500 Production	LFCSP:LEADFRM CHIP SCALE	OTH 260	-40 to 85C	320	272	Y
AD9680BCPZ-820 Production	LFCSP:LEADFRM CHIP SCALE	OTH 260	-40 to 85C	435	369.75	Y
AD9680BCPZRL7-1000 Production	64 ld LFCSP (9x9mm, 7.6mm exposed pad)	REEL 750	-40 to 85C	687.5	584.38	Y
AD9680BCPZRL7-1250 Production	LFCSP:LEADFRM CHIP SCALE	REEL 750	-40 to 85C	815	692.75	Y
AD9680BCPZRL7-500 Production	LFCSP:LEADFRM CHIP SCALE	REEL 750	-40 to 85C	320	272	Y
AD9680BCPZRL7-820 Production	LFCSP:LEADFRM CHIP SCALE	REEL 750	-40 to 85C	435	369.75	Y

Evaluation Boards

Part Number	Description	Price	RoHS
AD9234-1000EBZ	Evaluation board for the AD9234-1000 (Optimized for Full Analog Input Frequency Range)	895	Y
AD9234-500EBZ	Evaluation board for the AD9234-500 (Optimized for Full Analog Input Frequency Range)	795	Y
AD9234-LF1000EBZ	Evaluation board for AD9234-1000 (Up to 1GHz Input Bandwidth)	775	Y
AD9234-LF500EBZ	Evaluation board for AD9234-500 (Up to 1GHz Input Bandwidth)	575	Y
AD9680-1000EBZ	Evaluation board for the AD9980-1000 (Optimized for Full Analog Input Frequency Range)	995	Y
AD9680-1250EBZ	Evaluation Board for AD9680-1250 (Full Input Bandwidth)	1095	Y
AD9680-500EBZ	Evaluation board for the AD9680-500 (Optimized for Full Analog Input Frequency Range)	795	Y
AD9680-820EBZ	Evaluation board for the AD9680-820 (Optimized for Full Analog Input Frequency Range)	895	Y
AD9680-LF1000EBZ	Evaluation board for AD9680-1000 (Up to 1GHz Input Bandwidth)	775	Y
AD9680-LF500EBZ	Evaluation board for AD9680-500 (Up to 1GHz Input Bandwidth)	575	Y
AD9680-LF820EBZ	Evaluation board for AD9680-820 (Up to 1GHz Input Bandwidth)	675	Y
AD-FMCADC4-EBZ	4-Channel, 14-bit, 1GSPS Data Receiver Board	1699	Y
AD-FMCDAQ2-EBZ	AD-FMCDAQ2-EBZ Wideband RF data acquisition and signal synthesis module	1495	Y