ADCLK914 Ultrafast, SiGe, Open-Collector HVDS Clock/Data Buffer

The ADCLK914 is an ultrafast clock/data buffer fabricated on the Analog Devices, Inc., proprietary, complementary bipolar (XFCB-3) silicon-germanium (SiGe) process. The ADCLK914 features high voltage differential signaling (HVDS) outputs suitable for driving the latest Analog Devices high speed digital-to-analog converters (DACs). The ADCLK914 has a single, differential open-collector output.

The ADCLK914 buffer operates up to 7.5 GHz with a 160 ps propagation delay and adds only 110 fs random jitter (RJ).

The input has a center tapped, 100 Ω, on-chip termination resistor and accepts LVPECL, CML, CMOS, LVTTL, or LVDS (ac-coupled only). A VREF pin is available for biasing ac-coupled inputs.

The HVDS output stage is designed to directly drive 1.9 V each side into 50 Ω terminated to VCC for a total differential output swing of 3.8 V.

The ADCLK914 is available in a 16-lead LFCSP. It is specified for operation over the extended industrial temperature range of −40°C to +125°C.

Applications
  • Clock and data signal restoration
  • High speed converter clocking
  • Broadband communications
  • Cellular infrastructure
  • High speed line receivers
  • ATE and high performance instrumentation
  • Level shifting
  • Threshold detection

Features and Benefits
  • 7.5 GHz operating frequency
  • 160 ps propagation delay
  • 100 ps output rise/fall
  • 110 fs random jitter
  • On-chip input terminations
  • Extended industrial temperature range:
    −40°C to +125°C
  • 3.3 V power supply (VCC − VEE)
    • Clock & Timing
    RF & Microwave
    ADCLK914 IBIS Model
    Data Sheets
    Documentnote
    ADCLK914: Ultrafast, SiGe, Open-Collector HVDS Clock/Data Buffer Data Sheet (Rev. A)PDF 383 kB
    Application Notes
    Documentnote
    AN-501: Aperture Uncertainty and ADC System Performance (Rev. A)PDF 227 kB
    AN-756: Sampled Systems and the Effects of Clock Phase Noise and Jitter (Rev. 0)PDF 291.7 K
    AN-769: Generating Multiple Clock Outputs from the AD9540 (Rev. 0)PDF 0
    AN-939: Super-Nyquist Operation of the AD9912 Yields a High RF Output Signal (Rev. 0)PDF 221 kB
    AN-837: DDS-Based Clock Jitter Performance vs. DAC Reconstruction Filter Performance (Rev. 0)PDF 313 kB
    AN-823: Direct Digital Synthesizers in Clocking Applications Time (Rev. 0)PDF 115 kB
    AN-927: Determining if a Spur is Related to the DDS/DAC or to Some Other Source (For Example, Switching Supplies) (Rev. 0)PDF 170 kB
    AN-873: Lock Detect on the ADF4xxx Family of PLL Synthesizers (Rev. 0)PDF 207 kB
    AN-741: Little Known Characteristics of Phase Noise (Rev. 0)PDF 1679 kB
    User Guides
    Documentnote
    UG-058: Setting Up the Evaluation Board for the ADCLK914PDF 305 kB
    Frequently Asked Questions
    Documentnote
    Order Information
    Part NumberPackagePacking QtyTemp RangePrice 100-499Price 1000+RoHS
    ADCLK914BCPZ-R2 Production16 ld LFCSP (3x3mm, 1.50mm exposed pad)REEL 250-40 to 125C8.188.18Y
    ADCLK914BCPZ-R7 Production16 ld LFCSP (3x3mm, 1.50mm exposed pad)REEL 1500-40 to 125C06.95Y
    ADCLK914BCPZ-WP Production16 ld LFCSP (3x3mm, 1.50mm exposed pad)REEL 50-40 to 125C8.186.95Y
    Evaluation Boards
    Part NumberDescriptionPriceRoHS
    ADCLK914/PCBZEvaluation Board190Y
    Reference Materials
    ADCLK914: Ultrafast, SiGe, Open-Collector HVDS Clock/Data Buffer Data Sheet (Rev. A) adclk914
    ADCLK914 IBIS Model, Rev 3.0 adclk914
    AN-501: Aperture Uncertainty and ADC System Performance (Rev. A) ad9220
    AN-756: Sampled Systems and the Effects of Clock Phase Noise and Jitter (Rev. 0) ad9220
    AN-769: Generating Multiple Clock Outputs from the AD9540 (Rev. 0) ad9540
    AN-939: Super-Nyquist Operation of the AD9912 Yields a High RF Output Signal (Rev. 0) ad9540
    AN-837: DDS-Based Clock Jitter Performance vs. DAC Reconstruction Filter Performance (Rev. 0) ad9856
    AN-823: Direct Digital Synthesizers in Clocking Applications Time (Rev. 0) ad9856
    AN-927: Determining if a Spur is Related to the DDS/DAC or to Some Other Source (For Example, Switching Supplies) (Rev. 0) ad9540
    AN-769: 基于AD9540产生多时钟输出 (Rev. 0) ad9540
    AN-873: ADF4xxx系列PLL频率合成器的锁定检测 (Rev. 0) ad9540
    AN-939: 利用AD9912的超奈奎斯特频率操作得到高RF输出信号 (Rev. 0) ad9540
    AN-927: 确定杂散来源是DDS/DAC还是其他器件(例如开关电源)[中文版] (Rev. 0) ad9540
    AN-837: 基于DDS的时钟抖动性能与DAC重构滤波器性能的关系[中文版] (Rev. 0) ad9540
    AN-873: Lock Detect on the ADF4xxx Family of PLL Synthesizers (Rev. 0) ad9540
    AN-823: 时钟应用中的直接数字频率合成器[中文版] (Rev. 0) ad9540
    AN-756: 系统采样以及时钟相位噪声和抖动的影响[中文版] (Rev. 0) ad9540
    AN-501: 孔径不确定度与ADC系统性能[中文版] (Rev. A) ad9540
    AN-741: Little Known Characteristics of Phase Noise (Rev. 0) ad9221
    AN-741: 鲜为人知的相位噪声特性 ad9540
    UG-058: Setting Up the Evaluation Board for the ADCLK914 adclk914
    MT-008: 将振荡器相位噪声转换为时间抖动 adclk905
    RF Source Booklet adf9010
    Digital-to-Analog Converter ICs Solutions Bulletin, Volume 10, Issue 1 adclk905
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