ADCLK925 Ultrafast SiGe ECL Clock/Data Buffers

The ADCLK905 (one input, one output), ADCLK907 (dual one input, one output), and ADCLK925 (one input, two outputs) are ultrafast clock/data buffers fabricated on the Analog Devices, Inc., proprietary XFCB3 silicon germanium (SiGe) bipolar process.

The ADCLK905/ADCLK907/ADCLK925 feature full-swing emitter coupled logic (ECL) output drivers. For PECL (positive ECL) operation, bias VCC to the positive supply and VEE to ground. For NECL (negative ECL) operation, bias VCC to ground and VEE to the negative supply.

The buffers offer 95 ps propagation delay, 7.5 GHz toggle rate, 10 Gbps data rate, and 60 fs random jitter (RJ).

The inputs have center tapped, 100 Ω, on-chip termination resistors. A VREF pin is available for biasing ac-coupled inputs.

The ECL output stages are designed to directly drive 800 mV each side into 50 Ω terminated to VCC − 2 V for a total differential output swing of 1.6 V.

The ADCLK905/ADCLK907/ADCLK925 are available in 16-lead LFCSP packages.

Applications
  • Clock and data signal restoration and level shifting
  • Automated test equipment (ATE)
  • High speed instrumentation
  • High speed line receivers
  • Threshold detection
  • Converter clocking
Features and Benefits
  • 95 ps propagation delay
  • 7.5 GHz toggle rate
  • 60 ps typical output rise/fall
  • 60 fs random jitter (RJ)
  • On-chip terminations at both input pins
  • Extended industrial temperature range: −40°C to +125°C
  • 2.5 V to 3.3 V power supply (VCC − VEE)
    • Clock & Timing
    RF & Microwave
    ADCLK925 IBIS Model
    Reference Designs
    Data Sheets
    Documentnote
    ADCLK905/ADCLK907/ADCLK925: Ultrafast SiGe ECL Clock/Data Buffers Data Sheet (Rev. A)PDF 692.51 K
    Application Notes
    Documentnote
    AN-501: Aperture Uncertainty and ADC System Performance (Rev. A)PDF 227 kB
    AN-756: Sampled Systems and the Effects of Clock Phase Noise and Jitter (Rev. 0)PDF 291.7 K
    AN-769: Generating Multiple Clock Outputs from the AD9540 (Rev. 0)PDF 0
    AN-939: Super-Nyquist Operation of the AD9912 Yields a High RF Output Signal (Rev. 0)PDF 221 kB
    AN-837: DDS-Based Clock Jitter Performance vs. DAC Reconstruction Filter Performance (Rev. 0)PDF 313 kB
    AN-823: Direct Digital Synthesizers in Clocking Applications Time (Rev. 0)PDF 115 kB
    AN-927: Determining if a Spur is Related to the DDS/DAC or to Some Other Source (For Example, Switching Supplies) (Rev. 0)PDF 170 kB
    AN-873: Lock Detect on the ADF4xxx Family of PLL Synthesizers (Rev. 0)PDF 207 kB
    AN-741: Little Known Characteristics of Phase Noise (Rev. 0)PDF 1679 kB
    User Guides
    Documentnote
    UG-582: Evaluating the EVAL-CN0290-SDPZPDF 306 kB
    UG-006: Setting Up the Evaluation Board for the ADCLK905/ADCLK907/ADCLK925PDF 335 kB
    Frequently Asked Questions
    Documentnote
    Order Information
    Part NumberPackagePacking QtyTemp RangePrice 100-499Price 1000+RoHS
    ADCLK925BCPZ-R2 Production16 ld LFCSP (3x3mm, 1.5mm exposed pad)REEL 250-40 to 125C6.296.29Y
    ADCLK925BCPZ-R7 Production16 ld LFCSP (3x3mm, 1.5mm exposed pad)REEL 1500-40 to 125C05.35Y
    ADCLK925BCPZ-WP Production16 ld LFCSP (3x3mm, 1.5mm exposed pad)REEL 50-40 to 125C6.295.35Y
    Evaluation Boards
    Part NumberDescriptionPriceRoHS
    ADCLK925/PCBZEvaluation Board190Y
    Reference Materials
    ADCLK905/ADCLK907/ADCLK925: Ultrafast SiGe ECL Clock/Data Buffers Data Sheet (Rev. A) adclk905
    ADCLK925 IBIS Model adclk925
    CN0290 设计与集成文件 adclk905
    AN-501: Aperture Uncertainty and ADC System Performance (Rev. A) ad9220
    AN-756: Sampled Systems and the Effects of Clock Phase Noise and Jitter (Rev. 0) ad9220
    AN-769: Generating Multiple Clock Outputs from the AD9540 (Rev. 0) ad9540
    AN-939: Super-Nyquist Operation of the AD9912 Yields a High RF Output Signal (Rev. 0) ad9540
    AN-837: DDS-Based Clock Jitter Performance vs. DAC Reconstruction Filter Performance (Rev. 0) ad9856
    AN-823: Direct Digital Synthesizers in Clocking Applications Time (Rev. 0) ad9856
    AN-927: Determining if a Spur is Related to the DDS/DAC or to Some Other Source (For Example, Switching Supplies) (Rev. 0) ad9540
    AN-769: 基于AD9540产生多时钟输出 (Rev. 0) ad9540
    AN-873: ADF4xxx系列PLL频率合成器的锁定检测 (Rev. 0) ad9540
    AN-939: 利用AD9912的超奈奎斯特频率操作得到高RF输出信号 (Rev. 0) ad9540
    AN-927: 确定杂散来源是DDS/DAC还是其他器件(例如开关电源)[中文版] (Rev. 0) ad9540
    AN-837: 基于DDS的时钟抖动性能与DAC重构滤波器性能的关系[中文版] (Rev. 0) ad9540
    AN-873: Lock Detect on the ADF4xxx Family of PLL Synthesizers (Rev. 0) ad9540
    AN-823: 时钟应用中的直接数字频率合成器[中文版] (Rev. 0) ad9540
    AN-756: 系统采样以及时钟相位噪声和抖动的影响[中文版] (Rev. 0) ad9540
    AN-501: 孔径不确定度与ADC系统性能[中文版] (Rev. A) ad9540
    AN-741: Little Known Characteristics of Phase Noise (Rev. 0) ad9221
    AN-741: 鲜为人知的相位噪声特性 ad9540
    UG-582: Evaluating the EVAL-CN0290-SDPZ adclk905
    UG-006: Setting Up the Evaluation Board for the ADCLK905/ADCLK907/ADCLK925 adclk905
    MT-008: 将振荡器相位噪声转换为时间抖动 adclk905
    RF Source Booklet adf9010
    Digital-to-Analog Converter ICs Solutions Bulletin, Volume 10, Issue 1 adclk905
    CN-0290：扩展高性能锁相环的低频范围 adclk905
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