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ADCMP573 Ultrafast 3.3 V Single-Supply Comparator w/Reduced Swing PECL (RSPECL) Output Drivers

A flexible power supply scheme allows both devices to operate with a single 3.3 V positive supply and a −0.2 V to +1.2 V input signal range or with split input/output supplies to support a wider −0.2 V to +3.2 V input signal range and an independent range of output levels. 50 Ω on-chip termination resistors are provided at both inputs with the optional capability to be left open (on an individual pin basis) for applications requiring high impedance inputs. The CML output stage is designed to directly drive 400 mV into 50 Ω transmission lines terminated to between 3.3 V to 5.2 V. The RSPECL output stage is designed to drive 400 mV into 50 Ω terminated to VCCO − 2 V and is compatible with several commonly used PECL logic families. The comparator input stage offers robust protection against large input overdrive, and the outputs do not phase reverse when the valid input signal range is exceeded. High speed latch and programmable hysteresis features are also provided. The ADCMP572 and ADCMP573 are available in a 16-lead LFCSP package and have been characterized over an extended industrial temperature range of −40°C to +125°C.

The ADCMP572 and ADCMP573 are ultrafast comparators fabricated on Analog Devices’ proprietary XFCB3 Silicon Germanium (SiGe) bipolar process. The ADCMP572 features CML output drivers and latch inputs, and the ADCMP573 features reduced swing PECL (RSPECL) output drivers and latch inputs.

Both devices offer 150 ps propagation delay and 80 ps minimum pulse width for 10 Gbps operation with 200 fs rms random jitter (RJ). Overdrive and slew rate dispersion are typically less than 15 ps.

A flexible power supply scheme allows both devices to operate with a single 3.3 V positive supply and a −0.2 V to +1.2 V input signal range or with split input/output supplies to support a wider −0.2 V to +3.2 V input signal range and an independent range of output levels. 50 Ω on-chip termination resistors are provided at both inputs with the optional capability to be left open (on an individual pin basis) for applications requiring high impedance inputs.

The CML output stage is designed to directly drive 400 mV into 50 Ω transmission lines terminated to between 3.3 V to 5.2 V. The RSPECL output stage is designed to drive 400 mV into 50 Ω terminated to VCCO − 2 V and is compatible with several commonly used PECL logic families. The comparator input stage offers robust protection against large input overdrive, and the outputs do not phase reverse when the valid input signal range is exceeded. High speed latch and programmable hysteresis features are also provided.

The ADCMP572 and ADCMP573 are available in a 16-lead LFCSP package and have been characterized over an extended industrial temperature range of −40°C to +125°C.

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Reference Materials

• Product Selection Guide：Comparators Product Brochure 2007