ADSP-21477 High Performance Fourth Generation DSP
The fourth generation of SHARC® Processors, the ADSP-21477, includes low power floating point DSP products, which provide increased performance, hardware-based filter accelerators, audio and application-focused peripherals, and 2M Bit on Chip SRAM, capable of supporting a single chip solution. All devices are code-compatible with all prior SHARC Processors. These newest members of the fourth generation SHARC Processor family are based on a single-instruction, multiple-data (SIMD) core, which supports both 32-bit fixed-point and 32-/40-bit floating-point arithmetic formats and their low power make them particularly suitable for battery powered applications or where a higher ambient operating temperature is required.
The ADSP-21477 offers a very low power and high performance Processor – 200 MHz/1200 MFLOPs – in an 88-Ld LFCSP package. The low power architecture of the ADSP-21477 makes these products particularly well suited to address the automotive audio and industrial control market segments where low power is a requirement. In addition to its high core performance, the ADSP-21477 includes additional processing blocks such as FIR, IIR, and FFT accelerators to increase the total performance of the system. There is a new feature called Variable Instruction Set Architecture (VISA) that allows the code size to be decreased by 20% to 30% and increase the memory size availability. The fourth generation DSP allows the ability to connect to external memory by providing a glueless interface to 16-bit wide SDR SDRAMs.
Fourth-generation, ADSP-21477 SHARC Processors also integrate application-specific peripherals designed to simplify hardware design, minimize design risks, and ultimately reduce time to market. Grouped together, and broadly named the Digital Applications Interface (DAI), these functional blocks may be connected to each other or to external pins via the software-programmable Signal Routing Unit (SRU). The SRU is an innovative architectural feature that enables complete and flexible routing amongst DAI blocks. Peripherals connected through the SRU include but are not limited to serial ports, SPI ports, S/PDIF Tx/Rx, and an 8-Channel asynchronous sample rate converter block. The fourth generation SHARC allows data from the serial ports to be directly transferred to external memory by the DMA controller. Other peripherals such as UART and Two-Wire Interface are routed through a Digital Peripheral Interface (DPI).
Features and Benefits
| Processors & DSPIBIS Models |
Data Sheets
| Document | note |
| ADSP-21477/ADSP-21478/ADSP-21479 SHARC Processor Data Sheet (Rev. C) Documentation Errata | PDF 1950 kB |
