ADSP-TS101S 300 MHz TigerSHARC Processor with 6 Mbit on-chip SRAM

High performance 300 MHz, 3.3 ns instruction rate DSP core Executes eight 16-bit MACs with 40-bit accumulation or two 32-bit MACs with 80-bit accumulation per cycle Executes six single-precision floating point or twenty four 16-bit fixed point operations per cycle (1800 MFLOPS or 7.2 GOPS performance) 8-cycle instruction pipeline; 3-cycle fetch pipe and 5-cycle execution pipe Parallelism allows the execution of up to four 32-bit instructions per cycle

The ADSP-TS101S is the first member of the TigerSHARC Processor family. Targeted at numerous signal processing applications that rely on multiple processors working together to execute computationally-intensive real-time functions, ADI’s TigerSHARC processor is well-suited to video and communication markets, including the 3G cellular and broadband wireless base stations, as well as defense, medical imaging, industrial instrumentation. The ADSP-TS101S features a static superscaler architecture which combines RISC, VLIW and standard DSP functionality. Native support of fixed and floating point data types, coupled with the leading edge multiprocessing capabilities allows the TigerSHARC processor to offer unrivaled DSP performance. At a 300 MHz clock rate, the ADSP-TS101S offers the industry’s highest 16-bit fixed-point performance and a 32-bit floating 1024-point complex FFT time of 32.5 microseconds.

The ADSP-TS101S is available in both 19mm X 19mm and 27mm X 27mm inexpensive, plastic ball-grid array packages. The TigerSHARC is available for general purpose sampling today.

Features and Benefits

Static Superscalar architecture which supports 1, 8, 16 and 32-bit fixed point as well as floating point data processing
High performance 300 MHz, 3.3 ns instruction rate DSP core
6 Mbit on-chip SRAM internally organized in three banks with user-defined partitioning
14 channel, zero overhead DMA controller
Enhanced communications instruction set for wireless infrastructure applications allows for the TigerSHARC to offer complete base band processing

Three internal 128-bit wide internal buses providing a total memory bandwidth of 14.4 Gbytes per second
Software radio approach allows for the adoption of a single platform for multiple wireless telecommunication standards
Single instruction multiple-data (SIMD) operation supported by two computation blocks each with an ALU, multiplier, shifter and 32-word register file
Assembly and C language programmability

Processors & DSP

TigerSHARC Processors

IBIS Models

ADSP-TS101S IBIS Datafile BGA Package .ZIP

BSDL Model Files

Data Sheets

Document	note
ADSP-TS101S: TigerSHARC Embedded Processor, 300 MHz, 6 Mbits, Data Sheet (Rev. C) Documentation Errata	PDF 2276 kB

Application Notes

Document	note
EE-112: Class Implementation in Analog C++	PDF 31.54 K
EE-356: Emulator and Evaluation Hardware Troubleshooting Guide for CCES Users (Rev. 2) EE-356: Associated Files	PDF 779.29 K
EE-332: Cycle Counting and Profiling (Rev. 2) EE-332: Code example	PDF 142 kB
EE-120: Interfacing Assembly Language Programs to C	PDF
AN-911: A Detailed Guide to Powering the TigerSHARC Processors (Rev. 0)	PDF 239 kB
EE-330: Windows Vista Compatibility in VisualDSP++ 5.0 Development Tools (Rev. 1)	PDF 276 kB
EE-175: Emulator and Evaluation Hardware Troubleshooting Guide for VisualDSP++ Users (Rev. 14) EE-175: Associated Files	PDF 183 kB
EE-303: Using VisualDSP++® Thread-Safe Libraries with a Third-Party RTOS (Rev. 1)	PDF 56 kB
EE-273: Using the VisualDSP++ Command-Line Installer (Rev. 1)	PDF 96 kB
EE-261: Understanding Jitter Requirements of PLL-Based Processors (Rev. 1)	PDF 90 kB
EE-263: Parallel Implementation of Fixed-Point FFTs on TigerSHARC® Processors (Rev. 1)	PDF 148 kB
EE-217: Updating the ADSP-TS101S TigerSHARC® EZ-KIT Lite™ Firmware	PDF 73 kB
EE-202: Using the Expert Linker for Multiprocessor LDFs (Rev. 3) EE-202 Software Code	PDF 1186 kB
EE-241: SHARC® DSPs to TigerSHARC® Processors Code Porting Guide (Rev. 1) EE-241 Software Code	PDF 693 kB
EE-235: An Introduction to Scripting in VisualDSP++® (Rev. 1)	PDF 342 kB
EE-174: ADSP-TS101S TigerSHARC® Processor Boot Loader Kernels Operation	PDF 100 kB
EE-178: The ADSP-TS101S TigerSHARC® On-chip SDRAM Controller (Rev. 2)	PDF 613 kB
EE-176: Hardware Design Checklist For ADSP-TS101S TigerSHARC® Processors (Rev. 3)	PDF 334 kB
EE-210: SDRAM Selection and Configuration Guidelines for ADI Processors (Rev. 2)	PDF 241 kB
EE-68: Analog Devices JTAG Emulation Technical Reference (Rev. 10)	PDF 293 kB
EE-157: Explaining the Branch Target Buffer on the ADSP-TS101	PDF 22 kB
EE-169: Estimating Power For The ADSP-TS101S	PDF 114 kB
EE-167: Introduction to TigerSHARC® Multiprocessor Systems Using VisualDSP++™ EE-167 Software Code	PDF 578 kB
EE-128: DSP in C++: Calling Assembly Class Member Functions From C++	PDF 172 kB
EE-126: The ABCs of SDRAMemories (Rev. 1)	PDF 186 kB
EE-143: Understanding DMA on the ADSP-TS101 DMA Demonstration Code for EE-143	PDF 89 kB
EE-147: Tuning C Source Code for the TigerSHARC® DSP Compiler	PDF 194 kB
EE-110: A Quick Primar on ELF and DWARF File Formats	PDF 19 kB
EE-159: Initializing DSP System & Control Registers From C and C++	PDF 14 kB
EE-104: Setting Up Streams with the VisualDSP Debugger EE-104 Software Code	PDF 120 kB
EE-103: Performing Level Conversion Between 5v and 3.3v IC's	PDF 206 kB

Processor Manuals

Document	note
ADSP-TS101 TigerSHARC Processor Programming Reference (Rev. 1.1) Documentation Errata	PDF 2855 kB
ADSP-TS101 TigerSHARC Processor Hardware Reference (Rev. 1.1) Documentation Errata

Software Manuals

Document	note
VisualDSP++® 5.0 Assembler and Preprocessor Manual (Rev. 3.4)	PDF 3197 kB
VisualDSP++® 5.0 Loader and Utilities Manual (Rev. 2.5) Documentation Errata	PDF 2246 kB
VisualDSP++® 5.0 Licensing Guide (Rev. 1.4)	PDF 392 kB
VisualDSP++® 5.0 Kernel (VDK) Users Guide (Rev. 3.5)	PDF 2401 kB
VisualDSP++® 5.0 Linker and Utilities Manual (Rev. 3.5)	PDF 2290 kB
VisualDSP++® 5.0 Users Guide (Rev. 3.0)	PDF 2738 kB
VisualDSP++® 5.0 Quick Installation Reference Card (Rev. 3.1)	PDF 91 kB
VisualDSP++® 5.0 Getting Started Guide (Rev. 3.0) Documentation Errata	PDF 2035 kB
VisualDSP++® 5.0 Product Release Bulletin (Rev. 3.0)	PDF 774 kB
VisualDSP++® 5.0 C/C++ Compiler and Library Manual for TigerSHARC Processors (Rev. 4.1) Documentation Errata	PDF 3085 kB

Integrated Circuit Anomalies

Document	note
ADSP-TS101S TigerSHARC Anomaly List for Revision(s) 0.2, 0.4 (Rev. L)	PDF

Legacy Emulator Manuals

Document	note
Apex-ICE USB Emulator Hardware Installation Guide (Rev. 6.0)	PDF 605 kB
Summit-ICE PCI Emulator Hardware Installation Guide (Rev. 4)	PDF 508 kB

Product Highlight

Document	note
General-Purpose TigerSHARC Processor Product Brief	PDF 1101 kB

Evaluation Kit Manuals

Document	note
ADSP-TS101S EZ-KIT Lite® Manual (Rev. 2.1) Documentation Errata	PDF 1248 kB

Order Information

Part Number	Package	Packing Qty	Temp Range	Price 100-499	Price 1000+	RoHS
ADSP-TS101SAB1-000 Production	625 ball BGA	OTH 40	-40 to 85C	261.01	239.15	N
ADSP-TS101SAB1-100 Production	625 ball BGA	OTH 40	-40 to 85C	311.15	285.44	N
ADSP-TS101SAB1Z000 Production	625 ball BGA	OTH 40	-40 to 85C	232.76	213.27	Y
ADSP-TS101SAB1Z100 Production	625 ball BGA	OTH 40	-40 to 85C	277.48	254.54	Y
ADSP-TS101SAB2-000 Last Time Buy	484 ball BGA	OTH 84	-40 to 85C	261.01	239.15	N
ADSP-TS101SAB2-100 Production	484 ball BGA	OTH 84	-40 to 85C	311.15	285.44	N
ADSP-TS101SAB2Z000 Production	484 ball BGA	OTH 84	-40 to 85C	232.76	213.27	Y
ADSP-TS101SAB2Z100 Production	484 ball BGA	OTH 84	-40 to 85C	277.48	254.54	Y