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HMC6545 32 Gbps, Dual Channel, Advanced Linear Equalizer

The HMC6545 is a low power, high performance, fully programmable, dual-channel, asynchronous advanced linear equalizer that operates at data rates of up to 32 Gbps. The HMC6545 is protocol and data rate agnostic, and it can operate on the transmit path to predistort a transmitted signal to invert channel distortion or on the receiver path to equalize the distorted and attenuated received signal. The HMC6545 is effective in dealing with chromatic and polarization mode dispersion and intersymbol interference (ISI) caused by a wide variety of transmission media (backplane or fiber) and channel lengths.

The HMC6545 consists of an automatic gain control (AGC); dc offset correction circuitry; a 9-tap, 18 ps spaced feedforward equalizer (FFE); a summing node; and a linear programmable output driver. The input AGC linearly attenuates or amplifies the distorted input signal to generate a constant voltage at the input of the FFE. The 9-tap FFE is programmed via 2-wire interface to generate wide range frequency responses that are precursor or postcursor in nature for compensating signal impairments. After FFE tap coefficients are summed at the summing node, the signal is received by a linear output driver. DC offset correction circuitry is controlled either automatically or manually via Forward Error Correction (FEC).

All high speed differential inputs and outputs of the HMC6545 are current mode logic (CML) and terminated on chip with 50 Ω to the positive supply, 3.3 V, and can be dc-coupled or ac-coupled. The inputs and outputs of the HMC6545 can be operated either differentially or single-ended. The low power, high performance, and feature rich HMC6545 is packaged in a 5 mm × 5 mm, 32-lead LFCSP package. The device uses a single 3.3 V supply, eliminating external regulators. The HMC6545 operates over a −40°C to +95°C temperature range.

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Reference Materials

• Quality Documentation：Semiconductor Qualification Test Report: BiCMOS-D (QTR: 2014-00061)