The HMC959LC3 is a Divide-by-4 with Reset designed to support clock frequencies as high as 26 GHz. During normal operation, with the reset pin not asserted, the output toggles from its prior state on the positive edge of the clock. This results in a divide-by-four function of the clock input. Asserting the reset pin forces the Q output low regardless of the clock edge state (asynchronous reset assertion). Reversing the clock inputs allows for negative-edge triggered applications. The HMC959LC3 also features an output level control pin, VR, which allows for loss compensation or for signal level optimization.
All input signals to the HMC959LC3 are terminated with 50 Ω to ground on-chip, and may be either AC or DC coupled. Outputs can be connected directly to a 50 Ω terminated system, while DC blocking capacitors may be used if the terminating system is 50 Ω to a non-ground DC voltage. The HMC959LC3 operates from a single -3.3 V DC supply and is available in a ceramic RoHS-compliant 3x3 mm SMT package.
Applications
Features and Benefits
| Clock & Timing |
| Document | note |
| HMC959: Divide-By-4 with Reset & Programmable Output Voltage, 26 GHz Data Sheet | PDF 441.03 K |
| Part Number | Package | Packing Qty | Temp Range | Price 100-499 | Price 1000+ | RoHS |
|---|---|---|---|---|---|---|
| HMC959LC3 Production | LCC:CER LEADLESS CHIP CARR | OTH 50 | -40 to 85C | 116.23 | 94.15 | Y |
| HMC959LC3TR Production | LCC:CER LEADLESS CHIP CARR | REEL 100 | -40 to 85C | 116.23 | 94.15 | Y |
| HMC959LC3TR-R5 Production | LCC:CER LEADLESS CHIP CARR | REEL 500 | -40 to 85C | 116.23 | 94.15 | Y |
