HMC988 Programmable Clock Divider & Delay, DC - 4 GHz _ BDTIC a Leading Distributor in China

HMC988 Programmable Clock Divider & Delay, DC - 4 GHz

The HMC988LP3E is a an ultra low noise clock divider capable of dividing by 1/2/4/8/16/32. It is a versatile device with additional functionality including adjustable output phase, adjustable delay in 60 steps of ~ 20 ps, a clock synchronization function, and a clock invert option. Housed in a compact 3x3 mm SMT QFN package, the clock divider offers a high level of functionality. The device works with 3.3V supply or may be connected to 5V supply and utilize the optional on-chip regulator. This on-chip regulator may be bypassed. Up to 8 addressable HMC988LP3E devices can be used together on the SPI bus. The HMC988LP3E is ideally suited for data converter applications with extremely low phase noise requirements.

Applications

Features and Benefits

Programmable Clock Divide by 1/2/4/8/16/32
Delay Adjustment in Multiples of 1/2 Clock Cycles or in 60 Steps of 20 ps (Typ.)
-170 dBc/Hz Noise Floor @ 100 MHz Output

Up to 4 GHz Operation with 800 mVp-p LVPECL Output
3.3V Operation (or 5V Operation with Optional On-Chip Regulator for Best Performance)

Clock & Timing

Clock Generation & Distribution

Data Sheets

Document	note
HMC988 Data Sheet	PDF 1.39 M

Order Information

Part Number	Package	Packing Qty	Temp Range	Price 100-499	Price 1000+	RoHS
HMC988LP3E Production	16 ld QFN (3x3mm w/1.7mm ep)	OTH 50	-40 to 85C	10.12	8.19	Y
HMC988LP3ETR Production	16 ld QFN (3x3mm w/1.7mm ep)	REEL 500	-40 to 85C	10.12	8.19	Y