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Home > Fairchild Semiconductor > FET > FDG8850NZ

FDG8850NZ: 30V Dual N-Channel PowerTrench® MOSFET

This dual N-Channel logic level enhancement mode field effect transistors are produced using Fairchild’s proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. This device has been designed especially for low voltage applications as a replacement for bipolar digital transistors and small signal MOSFETs. Since bias resistors are not required, this dual digital FET can replace several different digital transistors, with different bias resistor values.

FDG8850NZ Datasheet
Features
  • Max rDS(on) = 0.4Ω at VGS = 4.5V, ID = 0.75A
  • Max rDS(on) = 0.5Ω at VGS = 2.7V, ID = 0.67A
  • Very low level gate drive requirements allowing operationin 3V circuits(VGS(th) <1.5V)
  • Very small package outline SC70-6
  • RoHS Compliant
Ordering Code
ProductProduct & Eco StatusUnit Price/1K OrderPacking Method ConventionPackage Marking Convention*
FDG8850NZFull Production Green as of Dec 2010  China RoHS$0.0954SC70 6L  -  1.1 x 1.25 x 2mm,  TAPE REEL
  • PDF SC70 6L  Drawing Last Update: Aug 2015
  • PDF SC70-6L T&R PACKING DRAWING Last Update: May 2013
  • PDF SOT Tape and Reel Packing Drawing Last Update: Oct 2016
Line 1&E (Space)
&E (Space)
&E (Space)
&. (Pin One)

Line 2&Y (Binary Calendar Year Coding)

Line 3&. (Pin One)
50&G (Weekly Date Code)

FDG8850NZ0.70.655150
Application Notes
  • AN-9034 Power MOSFET Avalanche Guideline Last Update : 05-Mar-2011
  • AN-7510 A New PSPICE Subcircuit for the Power MOSFET Featuring Global Temperature Options Last Update : 05-Mar-2011
  • AN-7533 A Revised MOSFET Model With Dynamic Temperature Compensation Last Update : 05-Mar-2011
  • AN-4163 Shielded Gate PowerTrench® MOSFET Datasheet Explanation Last Update : 23-Oct-2014
  • AN-9010 MOSFET Basics Last Update : 09-Sep-2013
  • AN-9065 FRFET® in Synchronous Rectification Last Update : 28-Jun-2014
  • AN-7515 A Combined Single-Pulse and Repetitive UIS Rating System Last Update : 03-Mar-2011
  • AN-9005 Driving and Layout Design for Fast Switching Super-Junction MOSFETs Last Update : 26-Nov-2014
  • AN-558 Introduction to Power MOSFETs and their Applications Last Update : 29-Mar-2016
  • FDG8850NZ Datasheet
    MOSFET Basics Last Update : 09-Sep-2013
    A Combined Single-Pulse and Repetitive UIS Rating System Last Update : 03-Mar-2011
    FRFET® in Synchronous Rectification Last Update : 28-Jun-2014
    Driving and Layout Design for Fast Switching Super-Junction MOSFETs Last Update : 26-Nov-2014
    Power MOSFET Avalanche Guideline Last Update : 05-Mar-2011
    SC70 6L  Drawing Last Update: Aug 2015
    SC70-6L T&R PACKING DRAWING Last Update: May 2013
    SOT Tape and Reel Packing Drawing Last Update: Oct 2016
    A New PSPICE Subcircuit for the Power MOSFET Featuring Global Temperature Options Last Update : 05-Mar-2011
    A Revised MOSFET Model With Dynamic Temperature Compensation Last Update : 05-Mar-2011
    Shielded Gate PowerTrench® MOSFET Datasheet Explanation Last Update : 23-Oct-2014
    Introduction to Power MOSFETs and their Applications Last Update : 29-Mar-2016
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