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Home > Fairchild Semiconductor > FET > FDS6670A

FDS6670A: Single N-Channel Logic Level PowerTrench® MOSFET

This N-Channel Logic Level MOSFET is produced using Fairchild Semiconductor’s advanced PowerTrench process that has been especially tailored to minimize the on-state resistance and yet maintain superior switching performance. These devices are well suited for low voltage and battery powered applications where low in-line power loss and fast switching are required.

FDS6670A Datasheet
Features
  • 13 A, 30 V
  • RDS(ON) = 8 mΩ @ VGS = 10 V
  • RDS(ON) = 10 mΩ @ VGS = 4.5 V
  • Fast switching speed
  • Low gate charge
  • High performance trench technology for extremely low RDS(ON)
  • High power and current handling capability
Ordering Code
ProductProduct & Eco StatusUnit Price/1K OrderPacking Method ConventionPackage Marking Convention*
FDS6670AFull Production Green as of Jan 2015  China RoHS$0.24SO 8L NB  -  1.75 x 3.9 x 4.9mm,  TAPE REEL
  • SO 8L NB  Drawing Last Update: Nov 2015
  • MO8A SON8, Packing Drawing Last Update: Oct 2015
  • SOIC 8L TR packing drawing Last Update: May 2013
  • SOIC 8L PACKING DRAWING Last Update: May 2013
  • SOIC 8L PACKING DRAWING Last Update: May 2013
  • SOIC Tape And Reel Packing Drawing Last Update: Jun 2016
Line 1$Y (Fairchild logo)
&Z (Plant Code)
&2 (2-Digit Date Code)
&K

Line 2FDS

Line 36670A

Application Notes
  • AN-4163 Shielded Gate PowerTrench® MOSFET Datasheet Explanation Last Update : 23-Oct-2014
  • AN-9034 Power MOSFET Avalanche Guideline Last Update : 05-Mar-2011
  • AN-7510 A New PSPICE Subcircuit for the Power MOSFET Featuring Global Temperature Options Last Update : 05-Mar-2011
  • AN-9010 MOSFET Basics Last Update : 09-Sep-2013
  • AN-9065 FRFET® in Synchronous Rectification Last Update : 28-Jun-2014
  • AN-7515 A Combined Single-Pulse and Repetitive UIS Rating System Last Update : 03-Mar-2011
  • AN-7533 A Revised MOSFET Model With Dynamic Temperature Compensation Last Update : 05-Mar-2011
  • AN-558 Introduction to Power MOSFETs and their Applications Last Update : 29-Mar-2016
  • AN-9005 Driving and Layout Design for Fast Switching Super-Junction MOSFETs Last Update : 26-Nov-2014
  • FDS6670A.pdf
    Power MOSFET Avalanche Guideline Last Update : 05-Mar-2011
    MOSFET Basics Last Update : 09-Sep-2013
    A Combined Single-Pulse and Repetitive UIS Rating System Last Update : 03-Mar-2011
    FRFET® in Synchronous Rectification Last Update : 28-Jun-2014
    Driving and Layout Design for Fast Switching Super-Junction MOSFETs Last Update : 26-Nov-2014
    SO 8L NB  Drawing Last Update: Nov 2015
    MO8A SON8, Packing Drawing Last Update: Oct 2015
    SOIC 8L TR packing drawing Last Update: May 2013
    SOIC 8L PACKING DRAWING Last Update: May 2013
    SOIC 8L PACKING DRAWING Last Update: May 2013
    SOIC Tape And Reel Packing Drawing Last Update: Jun 2016
    Shielded Gate PowerTrench® MOSFET Datasheet Explanation Last Update : 23-Oct-2014
    A New PSPICE Subcircuit for the Power MOSFET Featuring Global Temperature Options Last Update : 05-Mar-2011
    A Revised MOSFET Model With Dynamic Temperature Compensation Last Update : 05-Mar-2011
    Introduction to Power MOSFETs and their Applications Last Update : 29-Mar-2016
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