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Home > Fairchild Semiconductor > FET > FDZ1323NZ

FDZ1323NZ: 20V Common Drain N-Channel 2.5 V PowerTrench® WL-CSP MOSFET

This device is designed specifically as a single package solution for Li-Ion battery pack protection circuit and other ultra-portable applications. It features two common drain N-channel MOSFETs, which enables bidirectional current flow, on Fairchild’s advanced PowerTrench® process with state of the art“low pitch” WLCSP packaging process, the FDZ1323NZ minimizes both PCB space and rS1S2(on). This advanced WLCSP MOSFET embodies a breakthrough in packaging technology which enables the device to combine excellent thermal transfer characteristics, ultra-low profile packaging, lowgate charge and low rS1S2(on).

FDZ1323NZ Datasheet
Features
  • Max rS1S2(on) = 13 mΩ at VGS = 4.5 V, IS1S2 = 1 A
  • Max rS1S2(on) = 13 mΩ at VGS = 4 V, IS1S2 = 1 A
  • Max rS1S2(on) = 13 mΩ at VGS = 3.8 V, IS1S2 = 1 A
  • Max rS1S2(on) = 16 mΩ at VGS = 3.7 V, IS1S2 = 1 A
  • Max rS1S2(on) = 16 mΩ at VGS = 3.1 V, IS1S2 = 1 A
  • Max rS1S2(on) = 18 mΩ at VGS = 2.5 V, IS1S2 = 1 A
  • Occupies only 3 mm2 of PCB area
  • Ultra-thin package: less than 0.35 mm height when mounted to PCB
  • High power and current handling capability
  • HBM ESD protection level > 3.6kV (Note 3)
  • RoHS Compliant
Ordering Code
ProductProduct & Eco StatusUnit Price/1K OrderPacking Method ConventionPackage Marking Convention*
FDZ1323NZFull Production Green as of Mar 2014  China RoHS$0.4975WL-CSP 6L  -  .35 x 0 x 0mm,  TAPE REEL
  • WL-CSP 6L  Drawing Last Update: Jan 2015
  • WLCSP 2X3 Array Tape And Reel Packing Drawing Last Update: Nov 2016
  • WLCSP, Packing Drawing Last Update: Jul 2015
Line 1EC&K

Line 2&E (Space)
&2 (2-Digit Date Code)
&Z (Plant Code)

Line 3&. (Pin One)

Application Notes
  • AN-4163 Shielded Gate PowerTrench® MOSFET Datasheet Explanation Last Update : 23-Oct-2014
  • AN-9034 Power MOSFET Avalanche Guideline Last Update : 05-Mar-2011
  • AN-7510 A New PSPICE Subcircuit for the Power MOSFET Featuring Global Temperature Options Last Update : 05-Mar-2011
  • AN-9010 MOSFET Basics Last Update : 09-Sep-2013
  • AN-9065 FRFET® in Synchronous Rectification Last Update : 28-Jun-2014
  • AN-7515 A Combined Single-Pulse and Repetitive UIS Rating System Last Update : 03-Mar-2011
  • AN-7533 A Revised MOSFET Model With Dynamic Temperature Compensation Last Update : 05-Mar-2011
  • AN-558 Introduction to Power MOSFETs and their Applications Last Update : 29-Mar-2016
  • AN-9005 Driving and Layout Design for Fast Switching Super-Junction MOSFETs Last Update : 26-Nov-2014
  • FDZ1323NZ.pdf
    MOSFET Basics Last Update : 09-Sep-2013
    A Combined Single-Pulse and Repetitive UIS Rating System Last Update : 03-Mar-2011
    FRFET® in Synchronous Rectification Last Update : 28-Jun-2014
    Driving and Layout Design for Fast Switching Super-Junction MOSFETs Last Update : 26-Nov-2014
    Power MOSFET Avalanche Guideline Last Update : 05-Mar-2011
    WL-CSP 6L  Drawing Last Update: Jan 2015
    WLCSP 2X3 Array Tape And Reel Packing Drawing Last Update: Nov 2016
    WLCSP, Packing Drawing Last Update: Jul 2015
    A New PSPICE Subcircuit for the Power MOSFET Featuring Global Temperature Options Last Update : 05-Mar-2011
    A Revised MOSFET Model With Dynamic Temperature Compensation Last Update : 05-Mar-2011
    Shielded Gate PowerTrench® MOSFET Datasheet Explanation Last Update : 23-Oct-2014
    Introduction to Power MOSFETs and their Applications Last Update : 29-Mar-2016
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