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Home > Fairchild Semiconductor > FET > NDP6060L

NDP6060L: 60V N-Channel Logic Level Enhancement Mode Field Effect Transistor

These logic level N-Channel enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process has been especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulses in the avalanche and commutation modes. These devices are particularly suited for low voltage applications such as automotive, DC/DC converters, PWM motor controls, and other battery powered circuits where fast switching, low in-line power loss, and resistance to transients are needed.

NDP6060L Datasheet
Features
  • 48A, 60V. RDS(ON) = 0.025Ω @ VGS = 5V.
  • Low drive requirements allowing operation directly from logic drivers. VGS(TH) < 2.0V.
  • Critical DC electrical parameters specified at elevated temperature.
  • Rugged internal source-drain diode can eliminate the need for an external Zener diode transient suppressor.
  • 175°C maximum junction temperature rating.
  • High density cell design for extremely low RDS(ON).
  • TO-220 and TO-263 (D2PAK) package for both through hole and surface mount applications.
Ordering Code
ProductProduct & Eco StatusUnit Price/1K OrderPacking Method ConventionPackage Marking Convention*
NDP6060LFull Production ROHS Compliant as of 27-Feb-2006  China RoHS$0.9516TO-220 3L  -  4.83 x 10.16 x 8.89mm,  RAIL
  • TO-220 3L  Drawing Last Update: Nov 2015
  • TO220-3L, JEDEC VARIATION, PACKING DRAWING Last Update: Oct 2013
  • TO Tube Packing Drawing Last Update: Sep 2015
  • TO Vacuum Packing Drawing Last Update: Sep 2015
Line 1$Y (Fairchild logo)
&Z (Plant Code)
&3 (3-Digit Date Code)
&K

Line 2NDP6060L

Application Notes
  • AN-4163 Shielded Gate PowerTrench® MOSFET Datasheet Explanation Last Update : 23-Oct-2014
  • AN-9034 Power MOSFET Avalanche Guideline Last Update : 05-Mar-2011
  • AN-7510 A New PSPICE Subcircuit for the Power MOSFET Featuring Global Temperature Options Last Update : 05-Mar-2011
  • AN-9010 MOSFET Basics Last Update : 09-Sep-2013
  • AN-9065 FRFET® in Synchronous Rectification Last Update : 28-Jun-2014
  • AN-7515 A Combined Single-Pulse and Repetitive UIS Rating System Last Update : 03-Mar-2011
  • AN-7533 A Revised MOSFET Model With Dynamic Temperature Compensation Last Update : 05-Mar-2011
  • AN-558 Introduction to Power MOSFETs and their Applications Last Update : 29-Mar-2016
  • AN-9005 Driving and Layout Design for Fast Switching Super-Junction MOSFETs Last Update : 26-Nov-2014
  • NDP6060L.pdf
    Power MOSFET Avalanche Guideline Last Update : 05-Mar-2011
    MOSFET Basics Last Update : 09-Sep-2013
    A Combined Single-Pulse and Repetitive UIS Rating System Last Update : 03-Mar-2011
    FRFET® in Synchronous Rectification Last Update : 28-Jun-2014
    Driving and Layout Design for Fast Switching Super-Junction MOSFETs Last Update : 26-Nov-2014
    TO-220 3L  Drawing Last Update: Nov 2015
    TO220-3L, JEDEC VARIATION, PACKING DRAWING Last Update: Oct 2013
    TO Tube Packing Drawing Last Update: Sep 2015
    TO Vacuum Packing Drawing Last Update: Sep 2015
    Shielded Gate PowerTrench® MOSFET Datasheet Explanation Last Update : 23-Oct-2014
    A New PSPICE Subcircuit for the Power MOSFET Featuring Global Temperature Options Last Update : 05-Mar-2011
    A Revised MOSFET Model With Dynamic Temperature Compensation Last Update : 05-Mar-2011
    Introduction to Power MOSFETs and their Applications Last Update : 29-Mar-2016
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