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Home > Fairchild Semiconductor > FET > NDS332P

NDS332P: P-Channel Logic Level Enhancement Mode Field Effect Transistor

These P-Channel logic level enhancement mode power field effect transistors are produced using Fairchild's proprietary, high cell density, DMOS technology. This very high density process is especially tailored to minimize on-state resistance. These devices are particularly suited for low voltage applications such as notebook computer power management, portable electronics,     and other battery powered circuits where fast high-side switching, and low in-line power loss are needed in a very small outline surface mount package.

NDS332P Datasheet
Features
  • -1 A, -20 V, RDS(ON) = 0.41Ω @ VGS= -2.7 V, RDS(ON) = 0.3 Ω @ VGS = -4.5 V.
  • Very low level gate drive requirements allowing direct operation in 3V circuits. VGS(th) < 1.0V.
  • Proprietary package design using copper lead frame for superior thermal and electrical capabilities.
  • High density cell design for extremely low RDS(ON).
  • Exceptional on-resistance and maximum DC current capability.
  • Compact industry standard SOT-23 surface Mount package.
Ordering Code
ProductProduct & Eco StatusUnit Price/1K OrderPacking Method ConventionPackage Marking Convention*
NDS332PFull Production Green as of Dec 2011  China RoHS$0.0676SSOT 3L  -  1.12 x 2.92 x 1.4mm,  TAPE REEL
  • SSOT 3L  Drawing Last Update: May 2015
  • SOT Tape and Reel Packing Drawing Last Update: Oct 2016
Line 1&E (Space)
&Y (Binary Calendar Year Coding)

Line 2332&E (Space)
&G (Weekly Date Code)

Application Notes
  • AN-4163 Shielded Gate PowerTrench® MOSFET Datasheet Explanation Last Update : 23-Oct-2014
  • AN-9034 Power MOSFET Avalanche Guideline Last Update : 05-Mar-2011
  • AN-7510 A New PSPICE Subcircuit for the Power MOSFET Featuring Global Temperature Options Last Update : 05-Mar-2011
  • AN-9010 MOSFET Basics Last Update : 09-Sep-2013
  • AN-9065 FRFET® in Synchronous Rectification Last Update : 28-Jun-2014
  • AN-7515 A Combined Single-Pulse and Repetitive UIS Rating System Last Update : 03-Mar-2011
  • AN-7533 A Revised MOSFET Model With Dynamic Temperature Compensation Last Update : 05-Mar-2011
  • AN-558 Introduction to Power MOSFETs and their Applications Last Update : 29-Mar-2016
  • AN-9005 Driving and Layout Design for Fast Switching Super-Junction MOSFETs Last Update : 26-Nov-2014
  • NDS332P.pdf
    Power MOSFET Avalanche Guideline Last Update : 05-Mar-2011
    MOSFET Basics Last Update : 09-Sep-2013
    A Combined Single-Pulse and Repetitive UIS Rating System Last Update : 03-Mar-2011
    FRFET® in Synchronous Rectification Last Update : 28-Jun-2014
    Driving and Layout Design for Fast Switching Super-Junction MOSFETs Last Update : 26-Nov-2014
    SSOT 3L  Drawing Last Update: May 2015
    SOT Tape and Reel Packing Drawing Last Update: Oct 2016
    Shielded Gate PowerTrench® MOSFET Datasheet Explanation Last Update : 23-Oct-2014
    A New PSPICE Subcircuit for the Power MOSFET Featuring Global Temperature Options Last Update : 05-Mar-2011
    A Revised MOSFET Model With Dynamic Temperature Compensation Last Update : 05-Mar-2011
    Introduction to Power MOSFETs and their Applications Last Update : 29-Mar-2016
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