HSP50214B: Programmable Downconverter

The HSP50214B Programmable Downconverter converts digitized IF data into filtered baseband data which can be processed by a standard DSP microprocessor. The Programmable Downconverter (PDC) performs down conversion, decimation, narrowband low pass filtering, gain scaling, resampling, and Cartesian to Polar coordinate conversion.

The 14-bit sampled IF input is down converted to baseband by digital mixers and a quadrature NCO, as shown in the Block Diagram. A decimating (4 to 32) fifth order Cascaded Integrator-Comb (CIC) filter can be applied to the data before it is processed by up to 5 decimate-by-2 halfband filters. The halfband filters are followed by a 255-tap programmable FIR filter. The output data from the programmable FIR filter is scaled by a digital AGC before being re-sampled in a polyphase FIR filter. The output section can provide seven types of data: Cartesian (I, Q), polar (R, θ), filtered frequency (dθ/dt), Timing Error (TE), and AGC level in either parallel or serial format.

Key Features
  • Up to 65MSPS Front-End Processing Rates (CLKIN) and 55MHz Back-End Processing Rates (PROCCLK) Clocks May Be Asynchronous
  • Processing Capable of >100dB SFDR
  • Up to 255-Tap Programmable FIR
  • Overall Decimation Factor Ranging from 4 to 16384
  • Output Samples Rates to ≈ 12.94MSPS with Output Bandwidths to ≈ 982kHz Lowpass
  • 32-Bit Programmable NCO for Channel Selection and Carrier Tracking
  • Digital Resampling Filter for Symbol Tracking Loops and Incommensurate Sample-to-Output Clock Ratios
  • Digital AGC with Programmable Limits and Slew Rate to Optimize Output Signal Resolution; Fixed or Auto Gain Adjust
  • Serial, Parallel, and FIFO 16-Bit Output Modes
  • Cartesian to Polar Converter and Frequency Discriminator for AFC Loops and Demodulation of AM, FM, FSK, and DPSK
  • Input Level Detector for External I.F. AGC Support
  • Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
  • Single Channel Digital Software Radio Receivers
  • Base Station Rx's: AMPS, NA TDMA, GSM, and CDMA
  • Compatible with HSP50210 Digital Costas Loop for PSK Reception
  • Evaluation Platform Available
Typical Diagram
Application Notes
TitleTypeUpdatedSizeOther Languages
AN9892: Synchronizing HSP50214 (PDC) and HSP50215 (PUC)PDF13 Nov 201418 KB
AN9720: Calculating Maximum Processing Rates of the PDC (HSP50214, HSP50214A and HSP50214B)PDF13 Nov 2014356 KB
AN9657: Data Conversion Binary Code FormatsPDF13 Nov 201422 KB
Datasheets
TitleTypeUpdatedSizeOther Languages
HSP50214B DatasheetPDF14 Nov 20142.74 MB
Tech Briefs
TitleTypeUpdatedSizeOther Languages
TB349: Calculating the Maximum Output Sample Rate and Specifications Bandwidth of the HSP50214PDF19 Nov 201413 KB
Order Information
Part NumberPackage TypeWeight(g)PinsMSL RatingPeak Temp (°C)RoHS Status
HSP50214BVC120 Ld MQFP5.581204225
HSP50214BVCZ120 Ld MQFP5.581203245RoHS
HSP50214BVI120 Ld MQFP5.581204225
HSP50214BVIZ120 Ld MQFP5.581203245RoHS
HSP50214B Datasheet 14 Nov 2014
120 Ld MQFP HSP50214B
HSP50214B
AN9892: Synchronizing HSP50214 (PDC) and HSP50215 (PUC) 13 Nov 2014
AN9720: Calculating Maximum Processing Rates of the PDC (HSP50214, HSP50214A and HSP50214B) 13 Nov 2014
AN9657: Data Conversion Binary Code Formats 13 Nov 2014
TB349: Calculating the Maximum Output Sample Rate and Specifications Bandwidth of the HSP50214 19 Nov 2014