74AHC1G09GV: 2-input AND gate with open-drain output
The 74AHC1G09 is a high-speed Si-gate CMOS device.
The 74AHC1G09 provides the 2-input AND function with open-drain output.
The output of the 74AHC1G09 is an open drain and can be connected to other open-drain outputs to implement active-LOW, wired-OR or active-HIGH wired-AND functions. For digital operation this device must have a pull-up resistor to establish a logic HIGH level.
74AHC1G09GV: Product Block Diagram
Outline 3d SOT753
Data Sheets (1)
| Name/Description | Modified Date |
|---|---|
| 2-input AND gate with open-drain output (REV 2.0) PDF (67.0 kB) 74AHC1G09 [English] | 18 Dec 2007 |
Application Notes (6)
| Name/Description | Modified Date |
|---|---|
| Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English] | 13 Mar 2013 |
| Package lead inductance considerations in high-speed applications (REV 1.0) PDF (43.0 kB) AN212 [English] | 13 Mar 2013 |
| Ground and VCC Bounce of High-Speed Integrated Circuits (REV 1.0) PDF (25.0 kB) AN223 [English] | 13 Mar 2013 |
| Live Insertion Aspects of Philips Logic Families (REV 1.0) PDF (73.0 kB) AN252 [English] | 13 Mar 2013 |
| Pin FMEA for AHC/AHCT family (REV 1.0) PDF (52.0 kB) AN11106 [English] | 04 Nov 2011 |
| PicoGate Logic footprints (REV 1.0) PDF (87.0 kB) AN10161 [English] | 30 Oct 2002 |
Brochures (2)
| Name/Description | Modified Date |
|---|---|
| 電圧レベルシフタ (REV 1.1) PDF (3.1 MB) 75017511_JP [English] | 16 Feb 2015 |
| Voltage translation: How to manage mixed-voltage designs with NXP® level translators (REV 1.0) PDF (2.6 MB) 75017511 [English] | 20 May 2014 |
Package Information (1)
| Name/Description | Modified Date |
|---|---|
| plastic surface-mounted package; 5 leads (REV 1.0) PDF (243.0 kB) SOT753 [English] | 08 Feb 2016 |
Packing (1)
| Name/Description | Modified Date |
|---|---|
| Tape reel SMD; reversed product orientation 12NC ending 125 (REV 1.0) PDF (186.0 kB) SOT753_125 [English] | 29 Nov 2012 |
Supporting Information (1)
| Name/Description | Modified Date |
|---|---|
| MAR_SOT753 Topmark (REV 1.0) PDF (89.0 kB) MAR_SOT753 [English] | 03 Jun 2013 |
Ordering Information
| Product | Status | Family | VCC (V) | Function | Description | Type | Logic switching levels | Package version | Output drive capability (mA) | tpd (ns) | fmax (MHz) | No of bits | Power dissipation considerations | Tamb (Cel) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name | No of pins |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74AHC1G09GV | Active | AHC(T) | 2.0 - 5.5 | AND gates | open-drain | AND gates | CMOS | SOT753 | +/- 8 | 3.2 | 60 | 1 | low | -40~125 | 272 | 64.5 | 170 | TSOP5 | 5 |
Package Information
| Product ID | Package Description | Outline Version | Reflow/Wave Soldering | Packing | Product Status | Part NumberOrdering code(12NC) | Marking | Chemical Content | RoHS / Pb Free / RHF | LeadFree Conversion Date | EFR | IFR(FIT) | MTBF(hour) | MSL | MSL LF |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74AHC1G09GV | | SOT753 | Reel 7" Q3/T4, Reverse | Active | 74AHC1G09GV,125 (9352 857 16125) | A09 | 74AHC1G09GV |    | Always Pb-free | 84.9 | 6.62 | 1.51E8 | 1 | 1 |
- 2-input AND gate with open-drain output 74AHC1G09GW
- Sorting through the low voltage logic maze 74LVC_H_245A_Q100
- Package lead inductance considerations in high-speed applications 74LVC_H_245A_Q100
- Ground and VCC Bounce of High-Speed Integrated Circuits 74ALVC164245DGG-Q100
- Live Insertion Aspects of Philips Logic Families 74HC_T_245_Q100
- Pin FMEA for AHC/AHCT family 74AHC_T_245_Q100
- PicoGate Logic footprints NX3L4684
- 電圧レベルシフタ 74AVC16245DGG-Q100
- Voltage translation: How to manage mixed-voltage designs with NXP® level translators 74AVC16245DGG-Q100
- MAR_SOT753 Topmark 74LVC1G17_Q100
- plastic surface-mounted package; 5 leads 74LVC1G17_Q100
- Tape reel SMD; reversed product orientation 12NC ending 125 74LVC1G17_Q100
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- BAP70Q
