74AHC2G32DP: Dual 2-input OR gate
The 74AHC2G32; 74AHCT2G32 is a high-speed Si-gate CMOS device.
The 74AHC2G32; 74AHCT2G32 provides two 2-input OR gates.
74AHC2G32DP: Product Block Diagram
74AHC2G32DP: Block Diagram
Outline 3d SOT505-2
Data Sheets (1)
| Name/Description | Modified Date |
|---|---|
| Dual 2-input OR gate (REV 3.0) PDF (178.0 kB) 74AHC_AHCT2G32 [English] | 14 May 2013 |
Application Notes (6)
| Name/Description | Modified Date |
|---|---|
| Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English] | 13 Mar 2013 |
| Package lead inductance considerations in high-speed applications (REV 1.0) PDF (43.0 kB) AN212 [English] | 13 Mar 2013 |
| Ground and VCC Bounce of High-Speed Integrated Circuits (REV 1.0) PDF (25.0 kB) AN223 [English] | 13 Mar 2013 |
| Live Insertion Aspects of Philips Logic Families (REV 1.0) PDF (73.0 kB) AN252 [English] | 13 Mar 2013 |
| Pin FMEA for AHC/AHCT family (REV 1.0) PDF (52.0 kB) AN11106 [English] | 04 Nov 2011 |
| PicoGate Logic footprints (REV 1.0) PDF (87.0 kB) AN10161 [English] | 30 Oct 2002 |
Brochures (2)
| Name/Description | Modified Date |
|---|---|
| 電圧レベルシフタ (REV 1.1) PDF (3.1 MB) 75017511_JP [English] | 16 Feb 2015 |
| Voltage translation: How to manage mixed-voltage designs with NXP® level translators (REV 1.0) PDF (2.6 MB) 75017511 [English] | 20 May 2014 |
Package Information (1)
| Name/Description | Modified Date |
|---|---|
| plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm (REV 1.2) PDF (239.0 kB) SOT505-2 [English] | 08 Jun 2016 |
Packing (1)
| Name/Description | Modified Date |
|---|---|
| TSSOP8: Reel pack, reverse; SMD, 7" Q3/T4 Standard product orientation Orderable part number ending ,125 or... (REV 5.0) PDF (210.0 kB) SOT505-2_125 [English] | 02 May 2013 |
IBIS Model
- ahc2g32 IBIS model (REV 1.0) ibs AHC2G32 4/7/2013
Ordering Information
| Product | Status | Family | VCC (V) | Function | Logic switching levels | Description | Type | Output drive capability (mA) | Package version | tpd (ns) | fmax (MHz) | No of bits | Power dissipation considerations | Tamb (Cel) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name | No of pins |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74AHC2G32DP | Active | AHC(T) | 2.0 - 5.5 | OR gates | CMOS | dual 2-input OR gate | OR gates | +/- 8 | SOT505-2 | 3.2 | 60 | 2 | low | -40~125 | 218 | 20.9 | 106 | TSSOP8 | 8 |
Package Information
| Product ID | Package Description | Outline Version | Reflow/Wave Soldering | Packing | Product Status | Part NumberOrdering code(12NC) | Marking | Chemical Content | RoHS / Pb Free / RHF | LeadFree Conversion Date | EFR | IFR(FIT) | MTBF(hour) | MSL | MSL LF |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74AHC2G32DP | | SOT505-2 | Reel 7" Q3/T4, Reverse | Active | 74AHC2G32DP,125 (9352 746 67125) | A32 | 74AHC2G32DP |    | week 41, 2004 | 84.9 | 6.62 | 1.51E8 | 1 | 1 |
- Dual 2-input OR gate 74AHCT2G32GD
- Sorting through the low voltage logic maze 74LVC_H_245A_Q100
- Package lead inductance considerations in high-speed applications 74LVC_H_245A_Q100
- Ground and VCC Bounce of High-Speed Integrated Circuits 74ALVC164245DGG-Q100
- Live Insertion Aspects of Philips Logic Families 74HC_T_245_Q100
- Pin FMEA for AHC/AHCT family 74AHC_T_245_Q100
- PicoGate Logic footprints NX3L4684
- 電圧レベルシフタ 74AVC16245DGG-Q100
- Voltage translation: How to manage mixed-voltage designs with NXP® level translators 74AVC16245DGG-Q100
- ahc2g32 IBIS model 74AHC2G32GD
- plastic thin shrink small outline package; 8 leads; body width 3 mm; lead length 0.5 mm 74LVC3G17_Q100
- TSSOP8: Reel pack, reverse; SMD, 7" Q3/T4 Standard product orientation Orderable part number ending ,125 or... 74LVC3G17_Q100
- 74HC_T_2G32
- 74AHC_T_2G32
- XC7WT14
