74AHCT02PW: Quad 2-input NOR gate _ BDTIC a Leading Distributor in China

74AHCT02PW: Quad 2-input NOR gate

The 74AHC02; 74AHCT02 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A.

The 74AHC02; 74AHCT02 provides a quad 2-input NOR function.

74AHCT02PW: Product Block Diagram

Outline 3d SOT402-1

Data Sheets (1)

Name/Description	Modified Date
Quad 2-input NOR gate (REV 4.0) PDF (87.0 kB) 74AHC_AHCT02 [English]	21 May 2008

Application Notes (5)

Name/Description	Modified Date
Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English]	13 Mar 2013
Package lead inductance considerations in high-speed applications (REV 1.0) PDF (43.0 kB) AN212 [English]	13 Mar 2013
Ground and VCC Bounce of High-Speed Integrated Circuits (REV 1.0) PDF (25.0 kB) AN223 [English]	13 Mar 2013
Live Insertion Aspects of Philips Logic Families (REV 1.0) PDF (73.0 kB) AN252 [English]	13 Mar 2013
Pin FMEA for AHC/AHCT family (REV 1.0) PDF (52.0 kB) AN11106 [English]	04 Nov 2011

Brochures (2)

Name/Description	Modified Date
電圧レベルシフタ (REV 1.1) PDF (3.1 MB) 75017511_JP [English]	16 Feb 2015
Voltage translation: How to manage mixed-voltage designs with NXP® level translators (REV 1.0) PDF (2.6 MB) 75017511 [English]	20 May 2014

Selector Guides (2)

Name/Description	Modified Date
ロジック製品セレクションガイド... (REV 1.0) PDF (38.3 MB) LOGIC_SELECTION_GUIDE_2015_JP [English]	19 Nov 2015
Logic selection guide 2016 (REV 1.1) PDF (15.3 MB) 75017285 [English]	08 Jan 2015

Package Information (1)

Name/Description	Modified Date
plastic thin shrink small outline package; 14 leads; body width 4.4 mm (REV 1.0) PDF (285.0 kB) SOT402-1 [English]	08 Feb 2016

Packing (1)

Name/Description	Modified Date
TSSOP14; Reel pack; SMD, 13" Q1/T1 Standard product orientation Orderable part number ending ,118 or... (REV 1.0) PDF (217.0 kB) SOT402-1_118 [English]	08 Apr 2013

Supporting Information (1)

Name/Description	Modified Date
Footprint for wave soldering (REV 1.0) PDF (16.0 kB) SSOP-TSSOP-VSO-WAVE [English]	08 Oct 2009

IBIS Model

ahct02 IBIS model (REV 1.0) ibs AHCT02 4/7/2013

Ordering Information

Product	Status	Family	V_CC (V)	Function	Logic switching levels	Type	Description	Output drive capability (mA)	Package version	t_pd (ns)	f_max (MHz)	No of bits	Power dissipation considerations	T_amb (Cel)	R_th(j-a) (K/W)	Ψ_th(j-top) (K/W)	R_th(j-c) (K/W)	Package name	No of pins
74AHCT02PW	Active	AHC(T)	4.5 - 5.5	NOR gates	TTL	NOR gates	TTL enabled	+/- 8	SOT402-1	3.8	60	4	low	-40~125	138	1.0	8	TSSOP14	14

Package Information

Product ID	Package Description	Outline Version	Reflow/Wave Soldering	Packing	Product Status	Part NumberOrdering code(12NC)	Marking	Chemical Content	RoHS / Pb Free / RHF	LeadFree Conversion Date	EFR	IFR(FIT)	MTBF(hour)	MSL	MSL LF
74AHCT02PW		SOT402-1	SSOP-TSSOP-VSO-WAVE	Reel 13" Q1/T1	Active	74AHCT02PW,118 (9352 626 91118)	AHCT02	74AHCT02PW		week 10, 2005	84.9	6.62	1.51E8	1	1
74AHCT02PW		SOT402-1	SSOP-TSSOP-VSO-WAVE	Bulk Pack	Active	74AHCT02PW,112 (9352 626 91112)	AHCT02	74AHCT02PW		week 10, 2005	84.9	6.62	1.51E8	1	1

Quad 2-input NOR gate 74AHCT02PW

Sorting through the low voltage logic maze 74LVC_H_245A_Q100

Package lead inductance considerations in high-speed applications 74LVC_H_245A_Q100

Ground and VCC Bounce of High-Speed Integrated Circuits 74ALVC164245DGG-Q100

Live Insertion Aspects of Philips Logic Families 74HC_T_245_Q100

Pin FMEA for AHC/AHCT family 74AHC_T_245_Q100

電圧レベルシフタ 74AVC16245DGG-Q100

Voltage translation: How to manage mixed-voltage designs with NXP® level translators 74AVC16245DGG-Q100

ロジック製品セレクションガイド... 74LVC_H_245A_Q100

Logic selection guide 2016 74LVC_H_245A_Q100

ahct02 IBIS model 74AHCT02PW

plastic thin shrink small outline package; 14 leads; body width 4.4 mm 74LV164_Q100

SSOP-TSSOP-VSO-WAVE LPC1114FDH28

TSSOP14; Reel pack; SMD, 13" Q1/T1 Standard product orientation Orderable part number ending ,118 or... 74LV164_Q100

74LVC02A

74LV164

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