• 简体中文
• English

74AHCT164PW: 8-bit serial-in/parallel-out shift register

The 74AHC164; 74AHCT164 shift register is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7A.

The 74AHC164; 74AHCT164 input signals are 8-bit serial through one of two inputs (DSA or DSB); either input can be used as an active HIGH enable for data entry through the other input. Both inputs must be connected together or an unused input must be tied HIGH.

Data shifts one place to the right on each LOW-to-HIGH transition of the clock input (CP) and enters into output Q0, which is a logical AND of the two data inputs (DSA and DSB) that existed one set-up time prior to the rising clock edge.

A LOW-level on the master reset (MR) input overrides all other inputs and clears the register asynchronously, forcing all outputs LOW.

74AHCT164PW: Product Block Diagram

Outline 3d SOT402-1

Data Sheets (1)

Application Notes (5)

Brochures (2)

Selector Guides (2)

Package Information (1)

Packing (1)

Supporting Information (1)

IBIS Model

• ahct164 IBIS model (REV 1.0) ibs AHCT164 4/7/2013