74AHCT74BQ: Dual D-type flip-flop with set and reset; positive-edge trigger
The 74AHC74; 74AHCT74 is a high-speed Si-gate CMOS device and is pin compatible with Low-Power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A.
The 74AHC74; 74AHCT74 is a dual positive-edge triggered, D-type flip-flop with individual data inputs (D), clock inputs (CP), set inputs (SD) and reset inputs (RD). It also has complementary outputs (Q and Q).
The set and reset are asynchronous active LOW inputs that operate independent of the clock input. Information on the data input is transferred to the Q output on the LOW to HIGH transition of the clock pulse. The data inputs must be stable one set-up time prior to the LOW to HIGH clock transition for predictable operation.
Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.
74AHCT74BQ: Product Block Diagram
sot762-1_3d
Data Sheets (1)
Application Notes (5)
Selector Guides (2)
Package Information (1)
Packing (1)
IBIS Model
Ordering Information
Product | Status | Family | Function | VCC (V) | Logic switching levels | Description | Output drive capability (mA) | Package version | tpd (ns) | fmax (MHz) | Power dissipation considerations | Tamb (Cel) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name | No of pins |
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74AHCT74BQ | Active | AHC(T) | D-type flip-flops | 4.5 - 5.5 | TTL | TTL enabled | +/- 8 | SOT762-1 | 3.3 | 160 | low | -40~125 | 106 | 20.9 | 74 | DHVQFN14 | 14 |
Package Information
Product ID | Package Description | Outline Version | Reflow/Wave Soldering | Packing | Product Status | Part NumberOrdering code(12NC) | Marking | Chemical Content | RoHS / Pb Free / RHF | LeadFree Conversion Date | EFR | IFR(FIT) | MTBF(hour) | MSL | MSL LF |
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74AHCT74BQ | | SOT762-1 | | Reel 7" Q1/T1 | Active | 74AHCT74BQ,115
(9352 788 09115) | AHT74 | 74AHCT74BQ | | Always Pb-free | 84.9 | 6.62 | 1.51E8 | 1 | 1 |