The 74ALVC162334A is a 16-bit universal bus driver. Data flow is controlled by active LOW output enable (OE), active LOW latch enable (LE), and clock input (CP).
When LE is LOW, the A to Y data flow is transparent. When LE is HIGH and CP is held at LOW or HIGH, the data is latched; on the LOW to HIGH transient of CP, the A data is stored in the latch/flip-flop.
The 74ALVC162334A is designed with 30 Ω series resistors in both HIGH or LOW output stages.
When OE is LOW, the outputs are active. When OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does not affect the state of the latch/flip-flop.
To ensure the high-impedance state during power-up or power-down, OE should be tied to VCC through a pull-up resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Name/Description | Modified Date |
---|---|
16-bit registered driver with inverted register enable and 30 Ohm termination resistors (3-state) (REV 3.0) PDF (116.0 kB) 74ALVC162334A [English] | 13 Dec 2006 |
Name/Description | Modified Date |
---|---|
Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English] | 13 Mar 2013 |
Package lead inductance considerations in high-speed applications (REV 1.0) PDF (43.0 kB) AN212 [English] | 13 Mar 2013 |
A metastability primer (REV 1.0) PDF (40.0 kB) AN219 [English] | 13 Mar 2013 |
Ground and VCC Bounce of High-Speed Integrated Circuits (REV 1.0) PDF (25.0 kB) AN223 [English] | 13 Mar 2013 |
Live Insertion Aspects of Philips Logic Families (REV 1.0) PDF (73.0 kB) AN252 [English] | 13 Mar 2013 |
Interfacing 3 Volt and 5 Volt Applications (REV 1.0) PDF (63.0 kB) AN240 [English] | 15 Sep 1995 |
Name/Description | Modified Date |
---|---|
Low voltage CMOS family - LVC (REV 1.0) PDF (2.6 MB) 75017668 [English] | 10 Jul 2015 |
電圧レベルシフタ (REV 1.1) PDF (3.1 MB) 75017511_JP [English] | 16 Feb 2015 |
Voltage translation: How to manage mixed-voltage designs with NXP® level translators (REV 1.0) PDF (2.6 MB) 75017511 [English] | 20 May 2014 |
Name/Description | Modified Date |
---|---|
ロジック製品セレクションガイド... (REV 1.0) PDF (38.3 MB) LOGIC_SELECTION_GUIDE_2015_JP [English] | 19 Nov 2015 |
Logic selection guide 2016 (REV 1.1) PDF (15.3 MB) 75017285 [English] | 08 Jan 2015 |
Name/Description | Modified Date |
---|---|
plastic thin shrink small outline package; 48 leads; body width 6.1 mm (REV 1.0) PDF (467.0 kB) SOT362-1 [English] | 08 Feb 2016 |
Name/Description | Modified Date |
---|---|
TSSOP48; Reel pack; SMD, 13" Q1/T1 Standard product orientation Orderable part number ending ,118 or... (REV 5.0) PDF (242.0 kB) SOT362-1_118 [English] | 15 Apr 2013 |
Name/Description | Modified Date |
---|---|
Footprint for wave soldering (REV 1.0) PDF (16.0 kB) SSOP-TSSOP-VSO-WAVE [English] | 08 Oct 2009 |
Product | Status | Family | VCC (V) | Function | Logic switching levels | Description | Package version | Output drive capability (mA) | tpd (ns) | No of bits | Power dissipation considerations | Tamb (Cel) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name | No of pins |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
74ALVC162334ADGG | Active | ALVC | 1.65 - 3.6 | Latches/registered drivers | LVTTL | 16-bit registered driver with 30 ohm termination resistors (3-State) | SOT362-1 | +/- 12 | 6 | 16 | low | -40~85 | 82 | 1.9 | 36 | TSSOP48 | 48 |
Product ID | Package Description | Outline Version | Reflow/Wave Soldering | Packing | Product Status | Part NumberOrdering code(12NC) | Marking | Chemical Content | RoHS / Pb Free / RHF | LeadFree Conversion Date | EFR | IFR(FIT) | MTBF(hour) | MSL | MSL LF |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
74ALVC162334ADGG | SOT362-1 | SSOP-TSSOP-VSO-WAVE | Bulk Pack | Active | 74ALVC162334ADGG:1 (9352 673 01112) | 74ALVC162334A | 74ALVC162334ADGG | Always Pb-free | 123.8 | 3.87 | 2.58E8 | 1 | 1 | ||
Reel 13" Q1/T1 | Active | 74ALVC162334ADGG,1 (9352 673 01118) | 74ALVC162334A | 74ALVC162334ADGG | Always Pb-free | 123.8 | 3.87 | 2.58E8 | 1 | 1 |