74ALVC16836: 20-bit registered driver with inverted register enable (3-State)

The 74ALVC16836A is a 20-bit universal bus driver. Data flow is controlled by active low output enable (OE), active low latch enable (LE) and clock inputs (CP).

When LE is LOW, the A to Y data flow is transparent. When LE is HIGH and CP is held at LOW or HIGH, the data is latched; on the LOW to HIGH transient of CP the A-data is stored in the latch/flip-flop.

When OE is LOW the outputs are active. When OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the latch/flip-flop.

To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

Outline 3d SOT364-1

Data Sheets (1)

Name/Description	Modified Date
20-bit registered driver with inverted register enable (3-state) (REV 1.0) PDF (122.0 kB) 74ALVC16836A [English]	14 Mar 2014

Application Notes (6)

Name/Description	Modified Date
Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English]	13 Mar 2013
Package lead inductance considerations in high-speed applications (REV 1.0) PDF (43.0 kB) AN212 [English]	13 Mar 2013
A metastability primer (REV 1.0) PDF (40.0 kB) AN219 [English]	13 Mar 2013
Ground and VCC Bounce of High-Speed Integrated Circuits (REV 1.0) PDF (25.0 kB) AN223 [English]	13 Mar 2013
Live Insertion Aspects of Philips Logic Families (REV 1.0) PDF (73.0 kB) AN252 [English]	13 Mar 2013
Interfacing 3 Volt and 5 Volt Applications (REV 1.0) PDF (63.0 kB) AN240 [English]	15 Sep 1995

Brochures (3)

Name/Description	Modified Date
Low voltage CMOS family - LVC (REV 1.0) PDF (2.6 MB) 75017668 [English]	10 Jul 2015
電圧レベルシフタ (REV 1.1) PDF (3.1 MB) 75017511_JP [English]	16 Feb 2015
Voltage translation: How to manage mixed-voltage designs with NXP® level translators (REV 1.0) PDF (2.6 MB) 75017511 [English]	20 May 2014

Selector Guides (2)

Name/Description	Modified Date
ロジック製品セレクションガイド... (REV 1.0) PDF (38.3 MB) LOGIC_SELECTION_GUIDE_2015_JP [English]	19 Nov 2015
Logic selection guide 2016 (REV 1.1) PDF (15.3 MB) 75017285 [English]	08 Jan 2015

Package Information (1)

Name/Description	Modified Date
plastic thin shrink small outline package; 56 leads; body width 6.1 mm (REV 1.0) PDF (506.0 kB) SOT364-1 [English]	08 Feb 2016

Packing (1)

Name/Description	Modified Date
TSSOP56; Reel pack; SMD, 13" Q1/T1 Standard product orientation Orderable part number ending ,118 or... (REV 4.0) PDF (248.0 kB) SOT364-1_118 [English]	15 Apr 2013

Supporting Information (1)

Name/Description	Modified Date
Footprint for wave soldering (REV 1.0) PDF (16.0 kB) SSOP-TSSOP-VSO-WAVE [English]	08 Oct 2009

IBIS Model

alv836a IBIS model (REV 1.0) ibs ALV836A 4/7/2013

Ordering Information

Product	Status
74ALVC16836ADGG	Active

Package Information

Product ID	Package Description	Outline Version	Reflow/Wave Soldering	Packing	Product Status	Part NumberOrdering code(12NC)	Marking	Chemical Content	RoHS / Pb Free / RHF	LeadFree Conversion Date	EFR	IFR(FIT)	MTBF(hour)	MSL	MSL LF
74ALVC16836ADGG		SOT364-1	SSOP-TSSOP-VSO-WAVE	Reel 13" Q1/T1	Active	74ALVC16836ADGG,11 (9352 673 85118)	74ALVC16836A	74ALVC16836ADGG		week 40, 2005	123.8	3.87	2.58E8	1	1
74ALVC16836ADGG		SOT364-1	SSOP-TSSOP-VSO-WAVE	Bulk Pack	Active	74ALVC16836ADGG:11 (9352 673 85112)	74ALVC16836A	74ALVC16836ADGG		week 40, 2005	123.8	3.87	2.58E8	1	1