74ALVC573PW: Octal D-type transparent latch; 3-state
The 74ALVC573 is an octal D-type transparent latch featuring separate D-type inputs for each latch and 3-state true outputs for bus-oriented applications. A latch enable (LE) input and an outputs enable (OE) input are common to all latches.
When pin LE is HIGH, data at the D-inputs (pins D0 to D7) enters the latches. In this condition, the latches are transparent, that is, a latch output will change each time its corresponding D-input changes. When pin LE is LOW, the latches store the information that was present at the D-inputs one set-up time preceding the HIGH-to-LOW transition of pin LE.
When pin OE is LOW, the contents of the eight latches are available at the Q-outputs (pins Q0 to Q7). When pin OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of input pin OE does not affect the state of the latches.
The 74ALVC573 is functionally identical to the 74ALVC373, but has a different pin arrangement.
74ALVC573PW: Product Block Diagram
Outline 3d SOT360-1
Data Sheets (1)
| Name/Description | Modified Date |
|---|---|
| Octal D-type transparent latch; 3-state (REV 3.0) PDF (102.0 kB) 74ALVC573 [English] | 26 Oct 2007 |
Application Notes (6)
| Name/Description | Modified Date |
|---|---|
| Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English] | 13 Mar 2013 |
| Package lead inductance considerations in high-speed applications (REV 1.0) PDF (43.0 kB) AN212 [English] | 13 Mar 2013 |
| A metastability primer (REV 1.0) PDF (40.0 kB) AN219 [English] | 13 Mar 2013 |
| Ground and VCC Bounce of High-Speed Integrated Circuits (REV 1.0) PDF (25.0 kB) AN223 [English] | 13 Mar 2013 |
| Live Insertion Aspects of Philips Logic Families (REV 1.0) PDF (73.0 kB) AN252 [English] | 13 Mar 2013 |
| Interfacing 3 Volt and 5 Volt Applications (REV 1.0) PDF (63.0 kB) AN240 [English] | 15 Sep 1995 |
Brochures (3)
| Name/Description | Modified Date |
|---|---|
| Low voltage CMOS family - LVC (REV 1.0) PDF (2.6 MB) 75017668 [English] | 10 Jul 2015 |
| 電圧レベルシフタ (REV 1.1) PDF (3.1 MB) 75017511_JP [English] | 16 Feb 2015 |
| Voltage translation: How to manage mixed-voltage designs with NXP® level translators (REV 1.0) PDF (2.6 MB) 75017511 [English] | 20 May 2014 |
Selector Guides (2)
| Name/Description | Modified Date |
|---|---|
| ロジック製品セレクションガイド... (REV 1.0) PDF (38.3 MB) LOGIC_SELECTION_GUIDE_2015_JP [English] | 19 Nov 2015 |
| Logic selection guide 2016 (REV 1.1) PDF (15.3 MB) 75017285 [English] | 08 Jan 2015 |
Package Information (1)
| Name/Description | Modified Date |
|---|---|
| plastic thin shrink small outline package; 20 leads; body width 4.4 mm (REV 1.0) PDF (304.0 kB) SOT360-1 [English] | 08 Feb 2016 |
Packing (1)
| Name/Description | Modified Date |
|---|---|
| TSSOP20; Reel pack; SMD, 13" Q1/T1 Standard product orientation Orderable part number ending ,118 or... (REV 4.0) PDF (225.0 kB) SOT360-1_118 [English] | 15 Apr 2013 |
Supporting Information (1)
| Name/Description | Modified Date |
|---|---|
| Footprint for wave soldering (REV 1.0) PDF (16.0 kB) SSOP-TSSOP-VSO-WAVE [English] | 08 Oct 2009 |
IBIS Model
- alvc573 IBIS model (REV 1.0) ibs ALVC573 4/7/2013
Ordering Information
| Product | Status | Family | Function | VCC (V) | Description | Logic switching levels | Output drive capability (mA) | Package version | tpd (ns) | No of bits | Power dissipation considerations | Tamb (Cel) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name | No of pins |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74ALVC573PW | Active | ALVC | Latches/registered drivers | 1.65 - 3.6 | octal D-type transparent latch (3-state) | LVTTL | +/- 24 | SOT360-1 | 2.2 | 8 | low | -40~85 | 100 | 4.5 | 44.2 | TSSOP20 | 20 |
Package Information
| Product ID | Package Description | Outline Version | Reflow/Wave Soldering | Packing | Product Status | Part NumberOrdering code(12NC) | Marking | Chemical Content | RoHS / Pb Free / RHF | LeadFree Conversion Date | EFR | IFR(FIT) | MTBF(hour) | MSL | MSL LF |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74ALVC573PW | | SOT360-1 | SSOP-TSSOP-VSO-WAVE | Reel 13" Q1/T1 | Active | 74ALVC573PW,118 (9352 697 36118) | ALVC573 | 74ALVC573PW |    | week 5, 2005 | 123.8 | 3.87 | 2.58E8 | 1 | 1 |
| Bulk Pack | Active | 74ALVC573PW,112 (9352 697 36112) | ALVC573 | 74ALVC573PW | | week 5, 2005 | 123.8 | 3.87 | 2.58E8 | 1 | 1 |
- Octal D-type transparent latch; 3-state 74ALVC573PW
- Sorting through the low voltage logic maze 74LVC_H_245A_Q100
- Package lead inductance considerations in high-speed applications 74LVC_H_245A_Q100
- A metastability primer 74AHC573PW
- Ground and VCC Bounce of High-Speed Integrated Circuits 74ALVC164245DGG-Q100
- Live Insertion Aspects of Philips Logic Families 74HC_T_245_Q100
- Interfacing 3 Volt and 5 Volt Applications 74LVC377PW
- Low voltage CMOS family - LVC 74LVC_H_245A_Q100
- 電圧レベルシフタ 74AVC16245DGG-Q100
- Voltage translation: How to manage mixed-voltage designs with NXP® level translators 74AVC16245DGG-Q100
- ロジック製品セレクションガイド... 74LVC_H_245A_Q100
- Logic selection guide 2016 74LVC_H_245A_Q100
- alvc573 IBIS model 74ALVC573PW
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