74ALVCH16373DL: 2.5 V/3.3 V 16-bit D-type transparent latch; 3-state
The 74ALVCH16373 is 16-bit D-type transparent latch featuring separate D-type inputs for each latch and 3-state outputs for bus oriented applications.
Incorporates bus hold data inputs which eliminate the need for external pull-up or pull-down resistors to hold unused inputs.
One latch enable (LE) input and one output enable (OE) are provided per 8-bit section.
The 74ALVCH16373 consists of 2 sections of eight D-type transparent latches with 3-state true outputs. When LE is HIGH, data at the nDn inputs enter the latches. In this condition the latches are transparent, therefore a latch output will change each time its corresponding D-input changes.
When LE is LOW, the latches store the information that was present at the nDn inputs at a set-up time preceding the LOW-to-HIGH transition of LE. When OE is LOW, the contents of the eight latches are available at the outputs. When OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does not affect the state of the latches.
74ALVCH16373DL: Product Block Diagram
Outline 3d SOT370-1
Data Sheets (1)
| Name/Description | Modified Date |
|---|---|
| 2.5 V/3.3 V 16-bit D-type transparent latch; 3-state (REV 6.0) PDF (123.0 kB) 74ALVCH16373 [English] | 10 Jul 2012 |
Application Notes (6)
| Name/Description | Modified Date |
|---|---|
| Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English] | 13 Mar 2013 |
| Package lead inductance considerations in high-speed applications (REV 1.0) PDF (43.0 kB) AN212 [English] | 13 Mar 2013 |
| A metastability primer (REV 1.0) PDF (40.0 kB) AN219 [English] | 13 Mar 2013 |
| Ground and VCC Bounce of High-Speed Integrated Circuits (REV 1.0) PDF (25.0 kB) AN223 [English] | 13 Mar 2013 |
| Live Insertion Aspects of Philips Logic Families (REV 1.0) PDF (73.0 kB) AN252 [English] | 13 Mar 2013 |
| Interfacing 3 Volt and 5 Volt Applications (REV 1.0) PDF (63.0 kB) AN240 [English] | 15 Sep 1995 |
Brochures (3)
| Name/Description | Modified Date |
|---|---|
| Low voltage CMOS family - LVC (REV 1.0) PDF (2.6 MB) 75017668 [English] | 10 Jul 2015 |
| 電圧レベルシフタ (REV 1.1) PDF (3.1 MB) 75017511_JP [English] | 16 Feb 2015 |
| Voltage translation: How to manage mixed-voltage designs with NXP® level translators (REV 1.0) PDF (2.6 MB) 75017511 [English] | 20 May 2014 |
Selector Guides (2)
| Name/Description | Modified Date |
|---|---|
| ロジック製品セレクションガイド... (REV 1.0) PDF (38.3 MB) LOGIC_SELECTION_GUIDE_2015_JP [English] | 19 Nov 2015 |
| Logic selection guide 2016 (REV 1.1) PDF (15.3 MB) 75017285 [English] | 08 Jan 2015 |
Package Information (1)
| Name/Description | Modified Date |
|---|---|
| plastic shrink small outline package; 48 leads; body width 7.5 mm (REV 1.0) PDF (482.0 kB) SOT370-1 [English] | 08 Feb 2016 |
Packing (1)
| Name/Description | Modified Date |
|---|---|
| Standard product orientation 12NC ending 118 (REV 2.0) PDF (87.0 kB) SOT370-1_118 [English] | 19 Apr 2013 |
Supporting Information (2)
| Name/Description | Modified Date |
|---|---|
| Footprint for reflow soldering (REV 1.0) PDF (16.0 kB) SSOP-TSSOP-VSO-REFLOW [English] | 08 Oct 2009 |
| Footprint for wave soldering (REV 1.0) PDF (16.0 kB) SSOP-TSSOP-VSO-WAVE [English] | 08 Oct 2009 |
IBIS Model
- alvch16373 IBIS model (REV 1.0) ibs ALVCH16373 4/7/2013
Ordering Information
| Product | Status | Family | Function | VCC (V) | Logic switching levels | Description | Output drive capability (mA) | Package version | tpd (ns) | No of bits | Power dissipation considerations | Tamb (Cel) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name | No of pins |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74ALVCH16373DL | Active | ALVC | Latches/registered drivers | 2.3 - 3.6 | LVTTL | 16-bit D-type transparent latch with bus hold (3-state) | +/- 24 | SOT370-1 | 2.1 | 16 | low | -40~85 | 88 | 25.0 | SSOP48 | 48 |
Package Information
| Product ID | Package Description | Outline Version | Reflow/Wave Soldering | Packing | Product Status | Part NumberOrdering code(12NC) | Marking | Chemical Content | RoHS / Pb Free / RHF | LeadFree Conversion Date | EFR | IFR(FIT) | MTBF(hour) | MSL | MSL LF |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74ALVCH16373DL | | SOT370-1 | SSOP-TSSOP-VSO-REFLOW
SSOP-TSSOP-VSO-WAVE SSOP-TSSOP-VSO-REFLOW SSOP-TSSOP-VSO-WAVE | Reel 13" Q1/T1 | Active | 74ALVCH16373DL,118 (9352 604 43118) | ALVCH16373 | 74ALVCH16373DL |    | week 13, 2005 | 123.8 | 3.87 | 2.58E8 | 1 | 1 |
| Bulk Pack | Active | 74ALVCH16373DL,112 (9352 604 43112) | ALVCH16373 | 74ALVCH16373DL | | week 13, 2005 | 123.8 | 3.87 | 2.58E8 | 1 | 1 |
- 2.5 V/3.3 V 16-bit D-type transparent latch; 3-state 74ALVCH16373DL
- Sorting through the low voltage logic maze 74LVC_H_245A_Q100
- Package lead inductance considerations in high-speed applications 74LVC_H_245A_Q100
- A metastability primer 74AHC573PW
- Ground and VCC Bounce of High-Speed Integrated Circuits 74ALVC164245DGG-Q100
- Live Insertion Aspects of Philips Logic Families 74HC_T_245_Q100
- Interfacing 3 Volt and 5 Volt Applications 74LVC377PW
- Low voltage CMOS family - LVC 74LVC_H_245A_Q100
- 電圧レベルシフタ 74AVC16245DGG-Q100
- Voltage translation: How to manage mixed-voltage designs with NXP® level translators 74AVC16245DGG-Q100
- ロジック製品セレクションガイド... 74LVC_H_245A_Q100
- Logic selection guide 2016 74LVC_H_245A_Q100
- alvch16373 IBIS model 74ALVCH16373DL
- plastic shrink small outline package; 48 leads; body width 7.5 mm gtl2000dl
- Footprint for reflow soldering 74HC_T_595_Q100
- SSOP-TSSOP-VSO-WAVE LPC1114FDH28
- Standard product orientation 12NC ending 118 gtl2000dl
- 74ALVCH16373
- 74LVT162245B
