74ALVCH16374DL: 2.5 V/3.3 V 16-bit edge-triggered D-type flip-flop; 3-state

The 74ALVCH16374 is 16-bit edge-triggered flip-flop featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications.

Incorporates bus hold data inputs which eliminate the need for external pull-up or pull-down resistors to hold unused inputs.

The 74ALVCH16374 consists of 2 sections of eight edge-triggered flip-flops. A clock (CP) input and an output enable (OE) are provided per 8-bit section.

The flip-flops will store the state of their individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH CP transition.

When OE is LOW, the contents of the flip-flops are available at the outputs. When OE is HIGH, the outputs go the high-impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops.

74ALVCH16374DL: Product Block Diagram

Outline 3d SOT370-1

Data Sheets (1)

Name/Description	Modified Date
2.5 V/3.3 V 16-bit edge-triggered D-type flip-flop; 3-state (REV 5.0) PDF (120.0 kB) 74ALVCH16374 [English]	09 Jul 2012

Application Notes (5)

Name/Description	Modified Date
Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English]	13 Mar 2013
Package lead inductance considerations in high-speed applications (REV 1.0) PDF (43.0 kB) AN212 [English]	13 Mar 2013
Ground and VCC Bounce of High-Speed Integrated Circuits (REV 1.0) PDF (25.0 kB) AN223 [English]	13 Mar 2013
Live Insertion Aspects of Philips Logic Families (REV 1.0) PDF (73.0 kB) AN252 [English]	13 Mar 2013
Interfacing 3 Volt and 5 Volt Applications (REV 1.0) PDF (63.0 kB) AN240 [English]	15 Sep 1995

Brochures (2)

Name/Description	Modified Date
電圧レベルシフタ (REV 1.1) PDF (3.1 MB) 75017511_JP [English]	16 Feb 2015
Voltage translation: How to manage mixed-voltage designs with NXP® level translators (REV 1.0) PDF (2.6 MB) 75017511 [English]	20 May 2014

Selector Guides (2)

Name/Description	Modified Date
ロジック製品セレクションガイド... (REV 1.0) PDF (38.3 MB) LOGIC_SELECTION_GUIDE_2015_JP [English]	19 Nov 2015
Logic selection guide 2016 (REV 1.1) PDF (15.3 MB) 75017285 [English]	08 Jan 2015

Package Information (1)

Name/Description	Modified Date
plastic shrink small outline package; 48 leads; body width 7.5 mm (REV 1.0) PDF (482.0 kB) SOT370-1 [English]	08 Feb 2016

Packing (1)

Name/Description	Modified Date
Standard product orientation 12NC ending 118 (REV 2.0) PDF (87.0 kB) SOT370-1_118 [English]	19 Apr 2013

Supporting Information (2)

Name/Description	Modified Date
Footprint for reflow soldering (REV 1.0) PDF (16.0 kB) SSOP-TSSOP-VSO-REFLOW [English]	08 Oct 2009
Footprint for wave soldering (REV 1.0) PDF (16.0 kB) SSOP-TSSOP-VSO-WAVE [English]	08 Oct 2009

IBIS Model

alvch16374 IBIS model (REV 1.0) ibs ALVCH16374 4/7/2013

Ordering Information

Product	Status	Family	Function	V_CC (V)	Logic switching levels	Description	Package version	Output drive capability (mA)	t_pd (ns)	f_max (MHz)	Power dissipation considerations	T_amb (Cel)	R_th(j-a) (K/W)	Ψ_th(j-top) (K/W)	R_th(j-c) (K/W)	Package name	No of pins
74ALVCH16374DL	Active	ALVC	D-type flip-flops	1.2 - 3.6	TTL	positive-edge trigger (3-state)	SOT370-1	+/- 24	2.3	350	low	-40~85	88	25.0		SSOP48	48

Package Information

Product ID	Package Description	Outline Version	Reflow/Wave Soldering	Packing	Product Status	Part NumberOrdering code(12NC)	Marking	Chemical Content	RoHS / Pb Free / RHF	LeadFree Conversion Date	EFR	IFR(FIT)	MTBF(hour)	MSL	MSL LF
74ALVCH16374DL		SOT370-1	SSOP-TSSOP-VSO-REFLOW SSOP-TSSOP-VSO-WAVE SSOP-TSSOP-VSO-REFLOW SSOP-TSSOP-VSO-WAVE	Reel 13" Q1/T1	Active	74ALVCH16374DL,118 (9352 604 44118)	ALVCH16374	74ALVCH16374DL		week 13, 2005	123.8	3.87	2.58E8	1	1
74ALVCH16374DL		SOT370-1		Bulk Pack	Active	74ALVCH16374DL,112 (9352 604 44112)	ALVCH16374	74ALVCH16374DL		week 13, 2005	123.8	3.87	2.58E8	1	1