74ALVCH16500DGG: 18-bit universal bus transceiver (3-State)
The 74ALVCH16500 is a high-performance CMOS product. This device is an 18-bit universal transceiver featuring non-inverting 3-State bus compatible outputs in both send and receive directions. Data flow in each direction is controlled by output enable (OEAB and OE BA) latch enable (LEAB and LEBA)and clock (CP AB and CP BA) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is High. When LEAB is Low, the A data is latched if CP AB is held at a High or Low logic level. If LEAB is Low, the A-bus data is stored in the latch/flip-flop on the High-to-Low transition of CP AB. When OEAB is High, the outputs are active. When OEAB is Low, the outputs are in the high-impedance state.
Data flow for B-to-A is similar to that of A-to-B but uses OE BA LEBA and CP BA. The output enables are complimentary (OEAB is active High, and OE BA is active Low).
To ensure the high impedance state during power up or power down, OE BA should be tied to VCC through a pullup resistor and OEAB should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sinking/current-sourcing capability of the driver.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
74ALVCH16500DGG: Product Block Diagram
Outline 3d SOT364-1
Data Sheets (1)
| Name/Description | Modified Date |
|---|---|
| 18-bit universal bus transceiver (3-state) (REV 2.0) PDF (88.0 kB) 74ALVCH16500 [English] | 14 Mar 2014 |
Application Notes (5)
| Name/Description | Modified Date |
|---|---|
| Sorting through the low voltage logic maze (REV 1.0) PDF (72.0 kB) AN10156 [English] | 13 Mar 2013 |
| Package lead inductance considerations in high-speed applications (REV 1.0) PDF (43.0 kB) AN212 [English] | 13 Mar 2013 |
| Ground and VCC Bounce of High-Speed Integrated Circuits (REV 1.0) PDF (25.0 kB) AN223 [English] | 13 Mar 2013 |
| Live Insertion Aspects of Philips Logic Families (REV 1.0) PDF (73.0 kB) AN252 [English] | 13 Mar 2013 |
| Interfacing 3 Volt and 5 Volt Applications (REV 1.0) PDF (63.0 kB) AN240 [English] | 15 Sep 1995 |
Brochures (2)
| Name/Description | Modified Date |
|---|---|
| 電圧レベルシフタ (REV 1.1) PDF (3.1 MB) 75017511_JP [English] | 16 Feb 2015 |
| Voltage translation: How to manage mixed-voltage designs with NXP® level translators (REV 1.0) PDF (2.6 MB) 75017511 [English] | 20 May 2014 |
Selector Guides (2)
| Name/Description | Modified Date |
|---|---|
| ロジック製品セレクションガイド... (REV 1.0) PDF (38.3 MB) LOGIC_SELECTION_GUIDE_2015_JP [English] | 19 Nov 2015 |
| Logic selection guide 2016 (REV 1.1) PDF (15.3 MB) 75017285 [English] | 08 Jan 2015 |
Package Information (1)
| Name/Description | Modified Date |
|---|---|
| plastic thin shrink small outline package; 56 leads; body width 6.1 mm (REV 1.0) PDF (506.0 kB) SOT364-1 [English] | 08 Feb 2016 |
Packing (1)
| Name/Description | Modified Date |
|---|---|
| TSSOP56; Reel pack; SMD, 13" Q1/T1 Standard product orientation Orderable part number ending ,118 or... (REV 4.0) PDF (248.0 kB) SOT364-1_118 [English] | 15 Apr 2013 |
Supporting Information (1)
| Name/Description | Modified Date |
|---|---|
| Footprint for wave soldering (REV 1.0) PDF (16.0 kB) SSOP-TSSOP-VSO-WAVE [English] | 08 Oct 2009 |
IBIS Model
- alvch16500 IBIS model (REV 1.0) ibs ALVCH16500 4/7/2013
Ordering Information
| Product | Status | Family | Function | VCC (V) | Logic switching levels | Description | Package version | Output drive capability | tpd (ns) | No of bits | fmax (MHz) | Power dissipation considerations | Tamb (Cel) | Rth(j-a) (K/W) | Ψth(j-top) (K/W) | Rth(j-c) (K/W) | Package name | No of pins |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74ALVCH16500DGG | Active | ALVC | Transceivers | 1.65 - 3.6 | TTL | 18-bit universal bus transceiver with bus hold | SOT364-1 | +/- 24 | 2.9 | 18 | 150 | low | 93 | 21.0 | TSSOP56 | 56 |
Package Information
| Product ID | Package Description | Outline Version | Reflow/Wave Soldering | Packing | Product Status | Part NumberOrdering code(12NC) | Marking | Chemical Content | RoHS / Pb Free / RHF | LeadFree Conversion Date | EFR | IFR(FIT) | MTBF(hour) | MSL | MSL LF |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| 74ALVCH16500DGG | | SOT364-1 | SSOP-TSSOP-VSO-WAVE | Tube in Drypack | Active | 74ALVCH16500DGGS (9352 625 42512) | ALVCH16500 | 74ALVCH16500DGG |    | Always Pb-free | 123.8 | 3.87 | 2.58E8 | 1 | 1 |
| Reel 13" Q1/T1 in Drypack | Active | 74ALVCH16500DGGY (9352 625 42518) | ALVCH16500 | 74ALVCH16500DGG | | Always Pb-free | 123.8 | 3.87 | 2.58E8 | 1 | 1 | ||||
| Bulk Pack | Withdrawn | 74ALVCH16500DGG,11 (9352 625 42112) | ALVCH16500 | 74ALVCH16500DGG | | week 2, 2006 | 123.8 | 3.87 | 2.58E8 | 1 | 1 | ||||
| Reel 13" Q1/T1 | Withdrawn | 74ALVCH16500DGG:11 (9352 625 42118) | ALVCH16500 | 74ALVCH16500DGG | | week 2, 2006 | 123.8 | 3.87 | 2.58E8 | 1 | 1 |
- 18-bit universal bus transceiver (3-state) 74ALVCH16500DGG
- Sorting through the low voltage logic maze 74LVC_H_245A_Q100
- Package lead inductance considerations in high-speed applications 74LVC_H_245A_Q100
- Ground and VCC Bounce of High-Speed Integrated Circuits 74ALVC164245DGG-Q100
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